6 #include <soc/ramstage.h>
7 #include <soc/vr_config.h>
22 .voltage_limit = 1520,
25 .vr_config_enable = 1,
34 .voltage_limit = 1520,
37 .vr_config_enable = 1,
46 .voltage_limit = 1520,
49 .vr_config_enable = 1,
58 .voltage_limit = 1520,
74 #define VR_CONFIG(x, y) \
75 static const struct vr_lookup_item vr_config_##x##_##y[] =
76 #define VR_CONFIG_ICC(x) VR_CONFIG(x, ICC)
77 #define VR_CONFIG_LL(x) VR_CONFIG(x, LL)
78 #define VR_CONFIG_TDC(x) VR_CONFIG(x, TDC)
80 #define VR_REFITEM(x, y) { x, ARRAY_SIZE(vr_config_##x##_##y), vr_config_##x##_##y}
81 #define VR_REFITEM_ICC(x) VR_REFITEM(x, ICC)
82 #define VR_REFITEM_LL(x) VR_REFITEM(x, LL)
83 #define VR_REFITEM_TDC(x) VR_REFITEM(x, TDC)
86 const int tbl_entries,
93 for (
size_t i = 0; i < tbl_entries; i++) {
94 if (tbl[i].
mchid != mch_id)
97 for (
size_t j = 0; j < tbl[i].
num_items; j++) {
98 if (tbl[i].items[j].
tdp_min > tdp)
102 (tbl[i].items[j].
pl2_4_cfg != cfg->cpu_pl2_4_cfg))
617 int domain,
const struct vr_config *chip_cfg)
621 static uint16_t mch_id = 0, igd_id = 0;
646 vr_params->Psi3Enable[domain] = cfg->
psi3enable;
647 vr_params->Psi4Enable[domain] = cfg->
psi4enable;
648 vr_params->ImonSlope[domain] = cfg->
imon_slope;
664 printk(
BIOS_INFO,
" VrVoltageLimit: %u\n", vr_params->VrVoltageLimit[domain]);
667 vr_params->IccMax[domain] = cfg->
icc_max;
669 vr_params->IccMax[domain] =
get_sku_icc_max(domain, tdp, mch_id, igd_id);
677 domain, tdp, mch_id);
685 domain, tdp, mch_id);
696 domain, tdp, mch_id);
697 printk(
BIOS_INFO,
" TdcPowerLimit: %u\n", vr_params->TdcPowerLimit[domain]);
#define VR_CFG_ALL_DOMAINS_ICC(ia, gt)
#define VR_CFG_ALL_DOMAINS_TDC(ia, gt)
#define VR_CFG_ALL_DOMAINS_LOADLINE(ia, gt)
void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, int domain, const struct vr_config *chip_cfg)
static struct sdram_info params
#define VR_REFITEM_TDC(x)
static uint16_t load_table(const struct vr_lookup *tbl, const int tbl_entries, const int domain, const uint16_t tdp, const uint16_t mch_id)
#define VR_REFITEM_ICC(x)
static const struct vr_lookup vr_config_icc[]
static uint16_t get_sku_icc_max(const int domain, const uint16_t tdp, const uint16_t mch_id, const uint16_t igd_id)
static const struct vr_lookup vr_config_tdc[]
static const struct vr_lookup vr_config_ll[]
static const struct vr_config default_configs[NUM_VR_DOMAINS]
static uint16_t get_sku_voltagelimit(int domain)
#define printk(level,...)
uint32_t cpu_get_power_max(void)
DEVTREE_CONST struct device * pcidev_path_on_root(pci_devfn_t devfn)
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
#define BIOS_INFO
BIOS_INFO - Expected events.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
#define PCI_DID_INTEL_CML_H_4_2
#define PCI_DID_INTEL_CFL_ID_U
#define PCI_DID_INTEL_CML_S_P0P1_10_2
#define PCI_DID_INTEL_CFL_ID_S_WS_4
#define PCI_DID_INTEL_CFL_ID_S_S_6
#define PCI_DID_INTEL_CML_S_P0P1_8_2
#define PCI_DID_INTEL_WHL_ID_W_4
#define PCI_DID_INTEL_CML_S_G0G1_2
#define PCI_DID_INTEL_CML_S_G0G1_P0P1_6_2
#define PCI_DID_INTEL_CFL_ID_S_WS_8
#define PCI_DID_INTEL_CFL_ID_S_DT_2
#define PCI_DID_INTEL_CFL_ID_H_8
#define PCI_DID_INTEL_CFL_ID_S
#define PCI_DID_INTEL_CNL_ID_U
#define PCI_DID_INTEL_CFL_ID_S_DT_4
#define PCI_DID_INTEL_CFL_ID_H_4
#define PCI_DID_INTEL_CFL_ID_U_2
#define PCI_DID_INTEL_CML_ULT_6_2
#define PCI_DID_INTEL_CML_S_G0G1_4
#define PCI_DID_INTEL_CNL_ID_Y
#define PCI_DID_INTEL_CFL_ID_S_WS_6
#define PCI_DID_INTEL_CFL_ID_S_DT_8
#define PCI_DID_INTEL_CFL_ID_H
#define PCI_DID_INTEL_CML_ULT
#define PCI_DID_INTEL_CML_H_8_2
#define PCI_DID_INTEL_CFL_ID_S_S_8
#define PCI_DID_INTEL_CML_ULT_2_2
#define PCI_DID_INTEL_WHL_ID_W_2
#define PCI_DID_INTEL_CFL_ID_S_S_4
#define PCI_DID_INTEL_CML_H
enum chip_pl2_4_cfg pl2_4_cfg
uint16_t conf[NUM_VR_DOMAINS]
const struct vr_lookup_item * items