coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
devapc.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <soc/devapc.h>
5 #include <soc/devapc_common.h>
6 #include <soc/apusys_devapc.h>
7 
8 static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = {
9  /* 0 */
10  DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S",
12  DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-1",
14  DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-2",
16  DAPC_INFRA_AO_SYS0_ATTR("SPM_APB_S-4",
18  DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S",
20  DAPC_INFRA_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1",
22  DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_APB_S",
24  DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_APB_S",
26  DAPC_INFRA_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S",
28  DAPC_INFRA_AO_SYS0_ATTR("PERICFG_AO_APB_S",
30  /* 10 */
31  DAPC_INFRA_AO_SYS0_ATTR("GPIO_APB_S",
33  DAPC_INFRA_AO_SYS0_ATTR("TOPRGU_APB_S",
35  DAPC_INFRA_AO_SYS0_ATTR("DSP_IRQ_APB_S",
37  DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S",
39  DAPC_INFRA_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S",
41  DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S",
43  DAPC_INFRA_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S",
45  DAPC_INFRA_AO_SYS0_ATTR("PMIC_WRAP_APB_S",
47  DAPC_INFRA_AO_SYS0_ATTR("KP_APB_S",
49  DAPC_INFRA_AO_SYS0_ATTR("TOP_MISC_APB_S",
51  /* 20 */
52  DAPC_INFRA_AO_SYS0_ATTR("DVFSRC_APB_S",
54  DAPC_INFRA_AO_SYS0_ATTR("MBIST_AO_APB_S",
56  DAPC_INFRA_AO_SYS0_ATTR("HDMI_CEC_APB_S",
58  DAPC_INFRA_AO_SYS0_ATTR("HDMI_EDID_APB_S",
60  DAPC_INFRA_AO_SYS0_ATTR("HDMI_SCDC_APB_S",
62  DAPC_INFRA_AO_SYS0_ATTR("IRRX_APB_S",
64  DAPC_INFRA_AO_SYS0_ATTR("SYS_TIMER_APB_S",
66  DAPC_INFRA_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S",
68  DAPC_INFRA_AO_SYS0_ATTR("PMIF1_APB_S",
70  DAPC_INFRA_AO_SYS0_ATTR("PMICSPI_MST_APB_S",
72  /* 30 */
73  DAPC_INFRA_AO_SYS0_ATTR("TIA_APB_S",
75  DAPC_INFRA_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S",
77  DAPC_INFRA_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S",
79  DAPC_INFRA_AO_SYS0_ATTR("EFUSE_DEBUG_AO_APB_S",
81  DAPC_INFRA_AO_SYS0_ATTR("APXGPT_APB_S",
83  DAPC_INFRA_AO_SYS0_ATTR("SEJ_APB_S",
85  DAPC_INFRA_AO_SYS0_ATTR("AES_TOP0_APB_S",
87  DAPC_INFRA_AO_SYS0_ATTR("SECURITY_AO_APB_S",
89  DAPC_INFRA_AO_SYS0_ATTR("SPMI_MST_APB_S",
91  DAPC_INFRA_AO_SYS0_ATTR("DEBUG_CTRL_FMEM_AO_APB_S",
93  /* 40 */
94  DAPC_INFRA_AO_SYS0_ATTR("BCRM_FMEM_AO_APB_S",
96  DAPC_INFRA_AO_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S",
98  DAPC_INFRA_AO_SYS0_ATTR("PWM_APB_S",
100  DAPC_INFRA_AO_SYS0_ATTR("PMSR_APB_S",
102  DAPC_INFRA_AO_SYS0_ATTR("SRCLKEN_RC_APB_S",
104  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S",
106  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1",
108  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-2",
110  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-3",
112  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-4",
114  /* 50 */
115  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-5",
117  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-6",
119  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-7",
121  DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-8",
123  DAPC_INFRA_AO_SYS0_ATTR("APU_S_S",
125  DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-1",
127  DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-2",
129  DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3",
131  DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4",
133  DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5",
135  /* 60 */
136  DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S",
138  DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1",
140  DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2",
142  DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3",
144  DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4",
146  DAPC_INFRA_AO_SYS0_ATTR("L3C_S",
148  DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1",
150  DAPC_INFRA_AO_SYS0_ATTR("L3C_S-2",
152  DAPC_INFRA_AO_SYS0_ATTR("NNA0_S",
154  DAPC_INFRA_AO_SYS0_ATTR("NNA1_S",
156  /* 70 */
157  DAPC_INFRA_AO_SYS0_ATTR("NNA_APB_S",
159  DAPC_INFRA_AO_SYS0_ATTR("PCIE0_AXI_S",
161  DAPC_INFRA_AO_SYS0_ATTR("PCIE1_AXI_S",
163  DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB0_S",
165  DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB1_S",
167  DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB2_S",
169  DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB3_S",
171  DAPC_INFRA_AO_SYS0_ATTR("VIOSYS_APB4_S",
173 };
174 
175 static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[] = {
176  /* 0 */
177  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S",
179  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1",
181  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2",
183  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3",
185  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4",
187  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5",
189  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6",
191  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7",
193  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8",
195  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9",
197  /* 10 */
198  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10",
200  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11",
202  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12",
204  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-13",
206  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-14",
208  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-15",
210  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16",
212  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17",
214  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18",
216  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19",
218  /* 20 */
219  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-20",
221  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-21",
223  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-22",
225  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-23",
227  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-24",
229  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-25",
231  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-26",
233  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-27",
235  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-28",
237  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-29",
239  /* 30 */
240  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-30",
242  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-31",
244  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-32",
246  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-33",
248  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-34",
250  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-35",
252  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-36",
254  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-37",
256  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-38",
258  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-39",
260  /* 40 */
261  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-40",
263  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-41",
265  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-42",
267  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-43",
269  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-44",
271  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-45",
273  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-46",
275  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-47",
277  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-48",
279  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-49",
281  /* 50 */
282  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-50",
284  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-51",
286  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-52",
288  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-53",
290  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-54",
292  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-55",
294  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-56",
296  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-57",
298  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-58",
300  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-59",
302  /* 60 */
303  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-60",
305  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-61",
307  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-62",
309  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-63",
311  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-64",
313  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-65",
315  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-66",
317  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-67",
319  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-68",
321  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-69",
323  /* 70 */
324  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-70",
326  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-71",
328  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-72",
330  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-73",
332  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-74",
334  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-75",
336  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-76",
338  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-77",
340  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-78",
342  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-79",
344  /* 80 */
345  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-80",
347  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-81",
349  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-82",
351  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-83",
353  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-84",
355  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-85",
357  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-86",
359  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-87",
361  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-88",
363  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-89",
365  /* 90 */
366  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-90",
368  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-91",
370  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-92",
372  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-93",
374  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-94",
376  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-95",
378  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-96",
380  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-97",
382  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-98",
384  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-99",
386  /* 100 */
387  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-100",
389  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-101",
391  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-102",
393  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-103",
395  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-104",
397  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-105",
399  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-106",
401  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-107",
403  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-108",
405  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-109",
407  /* 110 */
408  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-110",
410  DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-111",
412  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S",
414  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-1",
416  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-2",
418  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-3",
420  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-4",
422  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-5",
424  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-6",
426  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-7",
428  /* 120 */
429  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-8",
431  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-9",
433  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-10",
435  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-11",
437  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-12",
439  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-13",
441  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-14",
443  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-15",
445  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-16",
447  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-17",
449  /* 130 */
450  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-18",
452  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-19",
454  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-20",
456  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-21",
458  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-22",
460  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-23",
462  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-24",
464  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-25",
466  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-26",
468  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-27",
470  /* 140 */
471  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-28",
473  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-29",
475  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-30",
477  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-31",
479  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-32",
481  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-33",
483  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-34",
485  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-35",
487  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-36",
489  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-37",
491  /* 150 */
492  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-38",
494  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-39",
496  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-40",
498  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-41",
500  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-42",
502  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-43",
504  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-44",
506  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-45",
508  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-46",
510  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-47",
512  /* 160 */
513  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-48",
515  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-49",
517  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-50",
519  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-51",
521  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-52",
523  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-53",
525  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-54",
527  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-55",
529  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-56",
531  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-57",
533  /* 170 */
534  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-58",
536  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-59",
538  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-60",
540  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-61",
542  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-62",
544  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-63",
546  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-64",
548  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-65",
550  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-66",
552  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-67",
554  /* 180 */
555  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-68",
557  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-69",
559  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-70",
561  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-71",
563  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-72",
565  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-73",
567  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-74",
569  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-75",
571  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-76",
573  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-77",
575  /* 190 */
576  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-78",
578  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-79",
580  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-80",
582  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-81",
584  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-82",
586  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-83",
588  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-84",
590  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-85",
592  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-86",
594  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-87",
596  /* 200 */
597  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-88",
599  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-89",
601  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-90",
603  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-91",
605  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-92",
607  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-93",
609  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-94",
611  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-95",
613  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-96",
615  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-97",
617  /* 210 */
618  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-98",
620  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-99",
622  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-100",
624  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-101",
626  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-102",
628  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-103",
630  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-104",
632  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-105",
634  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-106",
636  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-107",
638  /* 220 */
639  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-108",
641  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-109",
643  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-110",
645  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-111",
647  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-112",
649  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-113",
651  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-114",
653  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-115",
655  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-116",
657  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-117",
659  /* 230 */
660  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-118",
662  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-119",
664  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-120",
666  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-121",
668  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-122",
670  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-123",
672  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-124",
674  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-125",
676  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-126",
678  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-127",
680  /* 240 */
681  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-128",
683  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-129",
685  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-130",
687  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-131",
689  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-132",
691  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-133",
693  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-134",
695  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-135",
697  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-136",
699  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-137",
701  /* 250 */
702  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-138",
704  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-139",
706  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-140",
708  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-141",
710  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-142",
712  DAPC_INFRA_AO_SYS1_ATTR("MDP_S_S-143",
714 };
715 
716 static const struct apc_infra_peri_dom_4 infra_ao_sys2_devices[] = {
717  /* 0 */
718  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-144",
720  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-145",
722  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-146",
724  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-147",
726  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-148",
728  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-149",
730  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-150",
732  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-151",
734  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-152",
736  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-153",
738  /* 10 */
739  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-154",
741  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-155",
743  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-156",
745  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-157",
747  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-158",
749  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-159",
751  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-160",
753  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-161",
755  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-162",
757  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-163",
759  /* 20 */
760  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-164",
762  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-165",
764  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-166",
766  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-167",
768  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-168",
770  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-169",
772  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-170",
774  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-171",
776  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-172",
778  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-173",
780  /* 30 */
781  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-174",
783  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-175",
785  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-176",
787  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-177",
789  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-178",
791  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-179",
793  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-180",
795  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-181",
797  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-182",
799  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-183",
801  /* 40 */
802  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-184",
804  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-185",
806  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-186",
808  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-187",
810  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-188",
812  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-189",
814  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-190",
816  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-191",
818  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-192",
820  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-193",
822  /* 50 */
823  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-194",
825  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-195",
827  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-196",
829  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-197",
831  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-198",
833  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-199",
835  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-200",
837  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-201",
839  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-202",
841  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-203",
843  /* 60 */
844  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-204",
846  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-205",
848  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-206",
850  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-207",
852  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-208",
854  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-209",
856  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-210",
858  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-211",
860  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-212",
862  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-213",
864  /* 70 */
865  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-214",
867  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-215",
869  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-216",
871  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-217",
873  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-218",
875  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-219",
877  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-220",
879  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-221",
881  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-222",
883  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-223",
885  /* 80 */
886  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-224",
888  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-225",
890  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-226",
892  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-227",
894  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-228",
896  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-229",
898  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-230",
900  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-231",
902  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-232",
904  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-233",
906  /* 90 */
907  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-234",
909  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-235",
911  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-236",
913  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-237",
915  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-238",
917  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-239",
919  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-240",
921  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-241",
923  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-242",
925  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-243",
927  /* 100 */
928  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-244",
930  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-245",
932  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-246",
934  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-247",
936  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-248",
938  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-249",
940  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-250",
942  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-251",
944  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-252",
946  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-253",
948  /* 110 */
949  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-254",
951  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-255",
953  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-256",
955  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-257",
957  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-258",
959  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-259",
961  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-260",
963  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-261",
965  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-262",
967  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-263",
969  /* 120 */
970  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-264",
972  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-265",
974  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-266",
976  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-267",
978  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-268",
980  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-269",
982  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-270",
984  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-271",
986  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-272",
988  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-273",
990  /* 130 */
991  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-274",
993  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-275",
995  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-276",
997  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-277",
999  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-278",
1001  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-279",
1003  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-280",
1005  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-281",
1007  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-282",
1009  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-283",
1011  /* 140 */
1012  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-284",
1014  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-285",
1016  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-286",
1018  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-287",
1020  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-288",
1022  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-289",
1024  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-290",
1026  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-291",
1028  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-292",
1030  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-293",
1032  /* 150 */
1033  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-294",
1035  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-295",
1037  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-296",
1039  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-297",
1041  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-298",
1043  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-299",
1045  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-300",
1047  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-301",
1049  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-302",
1051  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-303",
1053  /* 160 */
1054  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-304",
1056  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-305",
1058  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-306",
1060  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-307",
1062  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-308",
1064  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-309",
1066  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-310",
1068  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-311",
1070  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-312",
1072  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-313",
1074  /* 170 */
1075  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-314",
1077  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-315",
1079  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-316",
1081  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-317",
1083  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-318",
1085  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-319",
1087  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-320",
1089  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-321",
1091  DAPC_INFRA_AO_SYS2_ATTR("MDP_S_S-322",
1093 };
1094 
1095 static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[] = {
1096  /* 0 */
1097  DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_PERI_AO_APB_S",
1099  DAPC_PERI_AO_SYS0_ATTR("BCRM_PERI_AO_APB_S",
1101  DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S",
1103  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S",
1105  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1",
1107  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2",
1109  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3",
1111  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4",
1113  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5",
1115  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6",
1117  /* 10 */
1118  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7",
1120  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8",
1122  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9",
1124  DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10",
1126  DAPC_PERI_AO_SYS0_ATTR("SSUSB_S",
1128  DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-1",
1130  DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-2",
1132  DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S",
1134  DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S",
1136  DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1",
1139  /* 20 */
1140  DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S",
1142  DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1",
1145  DAPC_PERI_AO_SYS0_ATTR("NOR_AXI_S",
1147  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S",
1149  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S",
1151  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S",
1153  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S",
1155  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S",
1157  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S",
1159  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S",
1161  /* 30 */
1162  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S",
1164  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S",
1166  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S",
1168  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S",
1170  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S",
1172  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S",
1174  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S",
1176  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S",
1178  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S",
1180  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S",
1182  /* 40 */
1183  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S",
1185  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S",
1187  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S",
1189  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S",
1191  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S",
1193  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S",
1195  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S",
1197  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S",
1199  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S",
1201  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S",
1203  /* 50 */
1204  DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S",
1206  DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S",
1208  DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S",
1210  DAPC_PERI_AO_SYS0_ATTR("CCIF3_AP_APB_S",
1212  DAPC_PERI_AO_SYS0_ATTR("CCIF3_MD_APB_S",
1214  DAPC_PERI_AO_SYS0_ATTR("CCIF4_AP_APB_S",
1216  DAPC_PERI_AO_SYS0_ATTR("CCIF4_MD_APB_S",
1218  DAPC_PERI_AO_SYS0_ATTR("CCIF5_AP_APB_S",
1220  DAPC_PERI_AO_SYS0_ATTR("CCIF5_MD_APB_S",
1222  DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB0_S",
1224  /* 60 */
1225  DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB1_S",
1227  DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_ACP_APB_S",
1229 };
1230 
1231 static const struct apc_infra_peri_dom_8 peri_ao_sys1_devices[] = {
1232  /* 0 */
1233  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S",
1235  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-1",
1237  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-2",
1239  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-3",
1241  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-4",
1243  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-5",
1245  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-6",
1247  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-7",
1249  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-8",
1251  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-9",
1253  /* 10 */
1254  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-10",
1256  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-11",
1258  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-12",
1260  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-13",
1262  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-14",
1264  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-15",
1266  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-16",
1268  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-17",
1270  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-18",
1272  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-19",
1274  /* 20 */
1275  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-20",
1277  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-21",
1279  DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-22",
1281 };
1282 
1283 static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[] = {
1284  /* 0 */
1285  DAPC_PERI2_AO_SYS0_ATTR("DEVICE_APC_PERI_AO2_APB_S",
1287  DAPC_PERI2_AO_SYS0_ATTR("BCRM_PERI_AO2_APB_S",
1289  DAPC_PERI2_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO2_APB_S",
1291  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB0_S",
1293  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB1_S",
1295  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB2_S",
1297  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB3_S",
1299  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB4_S",
1301  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB5_S",
1303  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB6_S",
1305  /* 10 */
1306  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB7_S",
1308  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB8_S",
1310  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB9_S",
1312  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB10_S",
1314  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB11_S",
1316  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB12_S",
1318  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB13_S",
1320  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB14_S",
1322  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_APB15_S",
1324  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB0_S",
1326  /* 20 */
1327  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB1_S",
1329  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB2_S",
1331  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB3_S",
1333  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB4_S",
1335  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB5_S",
1337  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB6_S",
1339  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB7_S",
1341  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB8_S",
1343  DAPC_PERI2_AO_SYS0_ATTR("BND_WEST_APB9_S",
1345  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB0_S",
1347  /* 30 */
1348  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB1_S",
1350  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB2_S",
1352  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB3_S",
1354  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB4_S",
1356  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB5_S",
1358  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB6_S",
1360  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB7_S",
1362  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB8_S",
1364  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB9_S",
1366  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB10_S",
1368  /* 40 */
1369  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB11_S",
1371  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB12_S",
1373  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB13_S",
1375  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB14_S",
1377  DAPC_PERI2_AO_SYS0_ATTR("BND_NORTH_APB15_S",
1379  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB0_S",
1381  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB1_S",
1383  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB2_S",
1385  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB3_S",
1387  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB4_S",
1389  /* 50 */
1390  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB5_S",
1392  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB6_S",
1394  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB7_S",
1396  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB8_S",
1398  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB9_S",
1400  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB10_S",
1402  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB11_S",
1404  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB12_S",
1406  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB13_S",
1408  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB14_S",
1410  /* 60 */
1411  DAPC_PERI2_AO_SYS0_ATTR("BND_SOUTH_APB15_S",
1413  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_NORTH_APB0_S",
1415  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_NORTH_APB1_S",
1417  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_NORTH_APB2_S",
1419  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_NORTH_APB3_S",
1421  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_NORTH_APB4_S",
1423  DAPC_PERI2_AO_SYS0_ATTR("BND_EAST_NORTH_APB5_S",
1425  DAPC_PERI2_AO_SYS0_ATTR("SYS_CIRQ_APB_S",
1427  DAPC_PERI2_AO_SYS0_ATTR("DEVICE_APC_INFRA_PDN_APB_S",
1429  DAPC_PERI2_AO_SYS0_ATTR("DEBUG_TRACKER_APB_S",
1431  /* 70 */
1432  DAPC_PERI2_AO_SYS0_ATTR("CCIF0_AP_APB_S",
1434  DAPC_PERI2_AO_SYS0_ATTR("CCIF0_MD_APB_S",
1436  DAPC_PERI2_AO_SYS0_ATTR("CCIF1_AP_APB_S",
1438  DAPC_PERI2_AO_SYS0_ATTR("CCIF1_MD_APB_S",
1440  DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_APB_S",
1442  DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_PDN_APB_S",
1444  DAPC_PERI2_AO_SYS0_ATTR("TRNG_APB_S",
1446  DAPC_PERI2_AO_SYS0_ATTR("GCPU_APB_S",
1448  DAPC_PERI2_AO_SYS0_ATTR("GCPU_NS_APB_S",
1450  DAPC_PERI2_AO_SYS0_ATTR("CQ_DMA_APB_S",
1452  /* 80 */
1453  DAPC_PERI2_AO_SYS0_ATTR("SRAMROM_APB_S",
1455  DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_APB_S",
1457  DAPC_PERI2_AO_SYS0_ATTR("ECC_TOP_APB_S",
1459  DAPC_PERI2_AO_SYS0_ATTR("GCE_APB_S",
1461  DAPC_PERI2_AO_SYS0_ATTR("GCE_M2_APB_S",
1463  DAPC_PERI2_AO_SYS0_ATTR("SYS_CIRQ1_APB_S",
1465  DAPC_PERI2_AO_SYS0_ATTR("SYS_CIRQ2_APB_S",
1467  DAPC_PERI2_AO_SYS0_ATTR("DEBUG_TRACKER_APB1_S",
1469  DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB0_S",
1471  DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB1_S",
1473  /* 90 */
1474  DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB2_S",
1476  DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB3_S",
1478  DAPC_PERI2_AO_SYS0_ATTR("INFRA_IOMMU_WRAP_APB4_S",
1480  DAPC_PERI2_AO_SYS0_ATTR("EMI_APB_S",
1482  DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_APB_S",
1484  DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_APB_S",
1486  DAPC_PERI2_AO_SYS0_ATTR("APDMA_APB_S",
1488  DAPC_PERI2_AO_SYS0_ATTR("DEBUG_TRACKER_APB2_S",
1490  DAPC_PERI2_AO_SYS0_ATTR("BCRM_INFRA_PDN_APB_S",
1492  DAPC_PERI2_AO_SYS0_ATTR("BCRM_PERI_PDN_APB_S",
1494  /* 100 */
1495  DAPC_PERI2_AO_SYS0_ATTR("BCRM_PERI_PDN2_APB_S",
1497  DAPC_PERI2_AO_SYS0_ATTR("DEVICE_APC_PERI_PDN_APB_S",
1499  DAPC_PERI2_AO_SYS0_ATTR("DEVICE_APC_PERI_PDN2_APB_S",
1501  DAPC_PERI2_AO_SYS0_ATTR("BCRM_FMEM_PDN_APB_S",
1503  DAPC_PERI2_AO_SYS0_ATTR("FAKE_ENGINE_1_S",
1505  DAPC_PERI2_AO_SYS0_ATTR("FAKE_ENGINE_0_S",
1507  DAPC_PERI2_AO_SYS0_ATTR("PERI_FAST_M_APB_S",
1509  DAPC_PERI2_AO_SYS0_ATTR("PERI_SLOW_M_APB_S",
1511  DAPC_PERI2_AO_SYS0_ATTR("EMI_SUB_INFRA_APB_S",
1513  DAPC_PERI2_AO_SYS0_ATTR("EMI_MPU_SUB_INFRA_APB_S",
1515  /* 110 */
1516  DAPC_PERI2_AO_SYS0_ATTR("DEVICE_MPU_PDN_SUB_INFRA_APB_S",
1518  DAPC_PERI2_AO_SYS0_ATTR("MBIST_PDN_SUB_INFRA_APB_S",
1520  DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_MEM_SUB_INFRA_APB_S",
1522  DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_AO_APB_S",
1524  DAPC_PERI2_AO_SYS0_ATTR("DEBUG_CTRL_SUB_INFRA_AO_APB_S",
1526  DAPC_PERI2_AO_SYS0_ATTR("BCRM_SUB_INFRA_PDN_APB_S",
1528  DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB1_S",
1530  DAPC_PERI2_AO_SYS0_ATTR("SSC_SUB_INFRA_APB2_S",
1532  DAPC_PERI2_AO_SYS0_ATTR("INFRACFG_AO_MEM_SUB_INFRA_APB_S",
1534  DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MM_S",
1536  /* 120 */
1537  DAPC_PERI2_AO_SYS0_ATTR("SUB_FAKE_ENGINE_MDP_S",
1539  DAPC_PERI2_AO_SYS0_ATTR("DEVICE_APC_SUB_INFRA_AO_APB_S",
1541 };
1542 
1543 static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[] = {
1544  /* 0 */
1547  DAPC_PERI_PAR_AO_SYS0_ATTR("UFS_S-1",
1549  DAPC_PERI_PAR_AO_SYS0_ATTR("UFS_S-2",
1551  DAPC_PERI_PAR_AO_SYS0_ATTR("UFS_S-3",
1553  DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC0_S",
1555  DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC1_S",
1557  DAPC_PERI_PAR_AO_SYS0_ATTR("MSDC2_S",
1559  DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE0_AHB_S",
1561  DAPC_PERI_PAR_AO_SYS0_ATTR("PCIE1_AHB_S",
1563  DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P1_S",
1565  /* 10 */
1566  DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P2_S",
1568  DAPC_PERI_PAR_AO_SYS0_ATTR("SSUSB_P3_S",
1570  DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S",
1572  DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S",
1574  DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S",
1576  DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S",
1578  DAPC_PERI_PAR_AO_SYS0_ATTR("UART3_APB_S",
1580  DAPC_PERI_PAR_AO_SYS0_ATTR("UART4_APB_S",
1582  DAPC_PERI_PAR_AO_SYS0_ATTR("UART5_APB_S",
1584  DAPC_PERI_PAR_AO_SYS0_ATTR("SPI0_APB_S",
1586  /* 20 */
1587  DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S",
1589  DAPC_PERI_PAR_AO_SYS0_ATTR("PERI_MBIST_PDN_APB_S",
1591  DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S",
1593  DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM1_APB_S",
1595  DAPC_PERI_PAR_AO_SYS0_ATTR("SNPS_MAC_APB_S",
1597  DAPC_PERI_PAR_AO_SYS0_ATTR("SPI1_APB_S",
1599  DAPC_PERI_PAR_AO_SYS0_ATTR("SPI2_APB_S",
1601  DAPC_PERI_PAR_AO_SYS0_ATTR("SPI3_APB_S",
1603  DAPC_PERI_PAR_AO_SYS0_ATTR("SPI4_APB_S",
1605  DAPC_PERI_PAR_AO_SYS0_ATTR("SPI5_APB_S",
1607  /* 30 */
1608  DAPC_PERI_PAR_AO_SYS0_ATTR("SPIS0_APB_S",
1610  DAPC_PERI_PAR_AO_SYS0_ATTR("SPIS1_APB_S",
1612  DAPC_PERI_PAR_AO_SYS0_ATTR("NFI_APB_S",
1614  DAPC_PERI_PAR_AO_SYS0_ATTR("NFIECC_APB_S",
1616  DAPC_PERI_PAR_AO_SYS0_ATTR("I2S_DMA_APB_S",
1618  DAPC_PERI_PAR_AO_SYS0_ATTR("I2S_DMA1_APB_S",
1620  DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_PDN_APB_S",
1622  DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S",
1624  DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S",
1626  DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB_S",
1628  /* 40 */
1629  DAPC_PERI_PAR_AO_SYS0_ATTR("NOR_APB_S",
1631  DAPC_PERI_PAR_AO_SYS0_ATTR("PERICFG2_AO_APB_S",
1633  DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_AO_APB_S",
1635  DAPC_PERI_PAR_AO_SYS0_ATTR("DEBUG_CTRL_PERI_PAR_AO_APB_S",
1637  DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_AO_APB_S",
1639 };
1640 
1641 static const enum domain_id domain_map[] = {
1644 };
1645 
1646 static inline void *getreg_domain(uintptr_t base, unsigned int offset,
1647  enum domain_id domain_id, unsigned int index)
1648 {
1649  return (void *)(base + offset + domain_id * 0x40 + index * 0x4);
1650 }
1651 
1652 static inline void *getreg(uintptr_t base, unsigned int offset)
1653 {
1654  return getreg_domain(base, offset, 0, 0);
1655 }
1656 
1658  enum devapc_perm_type perm)
1659 {
1660  uint32_t apc_register_index;
1661  uint32_t apc_set_index;
1662 
1663  apc_register_index = module / MOD_NO_IN_1_DEVAPC;
1664  apc_set_index = module % MOD_NO_IN_1_DEVAPC;
1665 
1666  clrsetbits32(getreg_domain(base, 0, domain_id, apc_register_index),
1667  0x3 << (apc_set_index * 2),
1668  perm << (apc_set_index * 2));
1669 }
1670 
1672 {
1673  int i, j;
1674 
1675  for (i = 0; i < ARRAY_SIZE(infra_ao_sys0_devices); i++)
1676  for (j = 0; j < ARRAY_SIZE(infra_ao_sys0_devices[i].d_permission); j++)
1679 
1680  for (i = 0; i < ARRAY_SIZE(infra_ao_sys1_devices); i++)
1681  for (j = 0; j < ARRAY_SIZE(infra_ao_sys1_devices[i].d_permission); j++)
1684 
1685  for (i = 0; i < ARRAY_SIZE(infra_ao_sys2_devices); i++)
1686  for (j = 0; j < ARRAY_SIZE(infra_ao_sys2_devices[i].d_permission); j++)
1689 }
1690 
1692 {
1693  int i, j;
1694 
1695  for (i = 0; i < ARRAY_SIZE(peri_ao_sys0_devices); i++)
1696  for (j = 0; j < ARRAY_SIZE(peri_ao_sys0_devices[i].d_permission); j++)
1699  /*
1700  * Extra apc setting.
1701  * Block debugsys to avoid privilege escalation.
1702  */
1703  if (!CONFIG(CONSOLE_SERIAL))
1706 
1707  for (i = 0; i < ARRAY_SIZE(peri_ao_sys1_devices); i++)
1708  for (j = 0; j < ARRAY_SIZE(peri_ao_sys1_devices[i].d_permission); j++)
1711 }
1712 
1714 {
1715  int i, j;
1716 
1717  for (i = 0; i < ARRAY_SIZE(peri2_ao_sys0_devices); i++)
1718  for (j = 0; j < ARRAY_SIZE(peri2_ao_sys0_devices[i].d_permission); j++)
1721 }
1722 
1724 {
1725  int i, j;
1726 
1727  for (i = 0; i < ARRAY_SIZE(peri_par_ao_sys0_devices); i++)
1728  for (j = 0; j < ARRAY_SIZE(peri_par_ao_sys0_devices[i].d_permission); j++)
1731 }
1732 
1734 {
1735  int reg_max;
1736  int d, i;
1737 
1739  for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++)
1740  for (i = 0; i < reg_max; i++)
1741  printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: %#x\n", d, i,
1743 
1745  for (d = 0; d < DOM_NUM_INFRA_AO_SYS1; d++)
1746  for (i = 0; i < reg_max; i++)
1747  printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO_SYS1)D%d_APC_%d: %#x\n", d, i,
1749 
1751  for (d = 0; d < DOM_NUM_INFRA_AO_SYS2; d++)
1752  for (i = 0; i < reg_max; i++)
1753  printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO_SYS2)D%d_APC_%d: %#x\n", d, i,
1755 
1756  printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO)MAS_SEC_0: %#x\n",
1758 
1759  printk(BIOS_DEBUG, "[DEVAPC] (INFRA_AO %#lx)DOM_REMAP_0_0: %#x\n",
1761 }
1762 
1764 {
1765  int reg_max;
1766  int d, i;
1767 
1769  for (d = 0; d < DOM_NUM_PERI_AO_SYS0; d++)
1770  for (i = 0; i < reg_max; i++)
1771  printk(BIOS_DEBUG, "[DEVAPC] (PERI_AO_SYS0)D%d_APC_%d: %#x\n", d, i,
1773 
1775  for (d = 0; d < DOM_NUM_PERI_AO_SYS1; d++)
1776  for (i = 0; i < reg_max; i++)
1777  printk(BIOS_DEBUG, "[DEVAPC] (PERI_AO_SYS1)D%d_APC_%d: %#x\n", d, i,
1779 
1780  printk(BIOS_DEBUG, "[DEVAPC] (PERI_AO)MAS_SEC_0: %#x\n",
1782 }
1783 
1785 {
1786  int reg_max;
1787  int d, i;
1788 
1790  for (d = 0; d < DOM_NUM_PERI2_AO_SYS0; d++)
1791  for (i = 0; i < reg_max; i++)
1792  printk(BIOS_DEBUG, "[DEVAPC] (PERI2_AO_SYS0)D%d_APC_%d: %#x\n", d, i,
1794 }
1795 
1797 {
1798  int reg_max;
1799  int d, i;
1800 
1802  for (d = 0; d < DOM_NUM_PERI_PAR_AO_SYS0; d++)
1803  for (i = 0; i < reg_max; i++)
1804  printk(BIOS_DEBUG, "[DEVAPC] (PERI_PAR_AO_SYS0)D%d_APC_%d: %#x\n", d,
1805  i, read32(getreg_domain(base, SYS0_D0_APC_0, d, i)));
1806 
1807  printk(BIOS_DEBUG, "[DEVAPC] (PERI_PAR_AO)MAS_SEC_0: %#x\n",
1809 }
1810 
1812 {
1813  printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n",
1815 }
1816 
1818 {
1819  printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_INFRA2_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n",
1821 }
1822 
1824 {
1825  printk(BIOS_DEBUG, "[DEVAPC] SCP:%#x ADSP:%#x Lock:%#x\n",
1829 }
1830 
1832 {
1833  /* Side band */
1835 
1836  /* Master Domain */
1838  SCP_SSPM_DOM, DOMAIN_2,
1839  CPU_EB_DOM, DOMAIN_2);
1840 
1841  /* Default APC Setting */
1843 
1844  /*
1845  * Domain Remap: MMSYS slave domain remap (4-bit to 2-bit)
1846  * 1. From domain 0 to domain 0 (no protection for all)
1847  * 2. From domain 1, 2, 4, 5 to domain 1 (forbidden for all)
1848  * 3. From domain 3 to domain 3
1849  * 4. others from XXX to domain 0
1850  */
1852  TWO_BIT_DOM_REMAP_0, DOMAIN_0,
1853  TWO_BIT_DOM_REMAP_1, DOMAIN_1,
1854  TWO_BIT_DOM_REMAP_2, DOMAIN_1,
1855  TWO_BIT_DOM_REMAP_3, DOMAIN_3,
1856  TWO_BIT_DOM_REMAP_4, DOMAIN_1,
1857  TWO_BIT_DOM_REMAP_5, DOMAIN_1);
1858  /*
1859  * Domain Remap: TINYSYS (3-bit to 4-bit)
1860  * 1. SCP from 3 to 3
1861  * 2. DSP from 4 to 4
1862  * 3. others from XXX to 15
1863  */
1865  FOUR_BIT_DOM_REMAP_0, DOMAIN_15,
1866  FOUR_BIT_DOM_REMAP_1, DOMAIN_15,
1867  FOUR_BIT_DOM_REMAP_2, DOMAIN_15,
1868  FOUR_BIT_DOM_REMAP_3, DOMAIN_3,
1869  FOUR_BIT_DOM_REMAP_4, DOMAIN_4,
1870  FOUR_BIT_DOM_REMAP_5, DOMAIN_15,
1871  FOUR_BIT_DOM_REMAP_6, DOMAIN_15,
1872  FOUR_BIT_DOM_REMAP_7, DOMAIN_15);
1873 }
1874 
1876 {
1877  /* Default APC Setting */
1879 
1880  /* Master Domain */
1882 
1883  /*
1884  * Domain Remap: TINYSYS slave domain remap (4-bit to 3-bit)
1885  * 1. From domain 0 to domain 0 (no protection for all)
1886  * 2. From domain 1 ~ 5 to domain 1 ~ 5
1887  * 3. others from XXX to domain 0 (no protection for all)
1888  */
1890  THREE_BIT_DOM_REMAP_0, DOMAIN_0,
1891  THREE_BIT_DOM_REMAP_1, DOMAIN_1,
1892  THREE_BIT_DOM_REMAP_2, DOMAIN_2,
1893  THREE_BIT_DOM_REMAP_3, DOMAIN_3,
1894  THREE_BIT_DOM_REMAP_4, DOMAIN_4,
1895  THREE_BIT_DOM_REMAP_5, DOMAIN_5);
1896 }
1897 
1899 {
1900  /* Default APC Setting */
1902 }
1903 
1905 {
1906  /* Side band */
1908  SSUSB_SEC, SECURE_TRANS,
1909  SSUSB2_SEC, SECURE_TRANS,
1910  SSUSB_P1_0_SEC, SECURE_TRANS,
1911  SSUSB_P1_1_SEC, SECURE_TRANS,
1912  SSUSB_P2_SEC, SECURE_TRANS,
1913  SSUSB_P3_SEC, SECURE_TRANS);
1914 
1915  /* Master Domain */
1917  PCIE0_DOM, DOMAIN_1,
1918  PCIE1_DOM, DOMAIN_1);
1919 
1920  /* Default APC Setting */
1922 }
1923 
1925 {
1926  /*
1927  * Domain Remap: TINYSYS to EMI (3-bit to 4-bit)
1928  * 1. SCP from 3 to 3
1929  * 2. DSP from 4 to 4
1930  * 3. others from XXX to 15
1931  */
1933  FOUR_BIT_DOM_REMAP_0, DOMAIN_15,
1934  FOUR_BIT_DOM_REMAP_1, DOMAIN_15,
1935  FOUR_BIT_DOM_REMAP_2, DOMAIN_15,
1936  FOUR_BIT_DOM_REMAP_3, DOMAIN_3,
1937  FOUR_BIT_DOM_REMAP_4, DOMAIN_4,
1938  FOUR_BIT_DOM_REMAP_5, DOMAIN_15,
1939  FOUR_BIT_DOM_REMAP_6, DOMAIN_15,
1940  FOUR_BIT_DOM_REMAP_7, DOMAIN_15);
1941 }
1942 
1944 {
1946  FOUR_BIT_DOM_REMAP_0, DOMAIN_15,
1947  FOUR_BIT_DOM_REMAP_1, DOMAIN_15,
1948  FOUR_BIT_DOM_REMAP_2, DOMAIN_15,
1949  FOUR_BIT_DOM_REMAP_3, DOMAIN_3,
1950  FOUR_BIT_DOM_REMAP_4, DOMAIN_4,
1951  FOUR_BIT_DOM_REMAP_5, DOMAIN_15,
1952  FOUR_BIT_DOM_REMAP_6, DOMAIN_15,
1953  FOUR_BIT_DOM_REMAP_7, DOMAIN_15);
1954 }
1955 
1957 {
1960 
1961  /* Let SCP_DOM and ADSP_DOM registers be read-only for security */
1962  write32(getreg(base, ONETIME_LOCK), 0x5);
1963 }
1964 
1965 struct devapc_init_ops {
1966  uintptr_t base;
1967  void (*init)(uintptr_t base);
1968  void (*dump)(uintptr_t base);
1969 } devapc_init[] = {
1977 };
1978 
1979 void dapc_init(void)
1980 {
1981  int i;
1982  uintptr_t devapc_ao_base;
1983 
1984  for (i = 0; i < ARRAY_SIZE(devapc_init); i++) {
1985  devapc_ao_base = devapc_init[i].base;
1986 
1987  /* Init dapc */
1988  write32(getreg(devapc_ao_base, AO_APC_CON), 0x0);
1989  write32(getreg(devapc_ao_base, AO_APC_CON), 0x1);
1990 
1991  /* Initialization */
1992  if (devapc_init[i].init)
1993  devapc_init[i].init(devapc_ao_base);
1994 
1995  /* Dump Setting */
1996  if (devapc_init[i].dump)
1997  devapc_init[i].dump(devapc_ao_base);
1998  }
1999 
2000  /* Set up APUSYS Permission */
2002 }
void start_apusys_devapc(void)
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
static uint32_t read32(const void *addr)
Definition: mmio.h:22
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define DIV_ROUND_UP(x, y)
Definition: helpers.h:60
#define printk(level,...)
Definition: stdlib.h:16
#define FORBIDDEN3
Definition: devapc_common.h:34
#define NO_PROTECTION3
Definition: devapc_common.h:47
#define FORBIDDEN12
Definition: devapc_common.h:41
#define FORBIDDEN11
Definition: devapc_common.h:40
#define FORBIDDEN14
Definition: devapc_common.h:43
#define FORBIDDEN13
Definition: devapc_common.h:42
#define FORBIDDEN7
Definition: devapc_common.h:38
#define FORBIDDEN10
Definition: devapc_common.h:39
#define FORBIDDEN15
Definition: devapc_common.h:44
#define FORBIDDEN2
Definition: devapc_common.h:33
#define NO_PROTECTION2
Definition: devapc_common.h:46
@ CONFIG
Definition: dsi_common.h:201
static size_t offset
Definition: flashconsole.c:16
static void init(struct device *dev)
This function is the driver entry point for the init phase of the PCI bus allocator.
Definition: i210.c:181
#define SET32_BITFIELDS(addr,...)
Definition: mmio.h:201
#define clrsetbits32(addr, clear, set)
Definition: mmio.h:16
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
void dapc_init(void)
Definition: devapc.c:1306
#define DAPC_INFRA_AO_SYS0_ATTR(...)
Definition: devapc.h:80
@ DEVAPC_DEBUGSYS_INDEX
Definition: devapc.h:76
@ SECURE_TRANS
Definition: devapc.h:28
devapc_perm_type
Definition: devapc.h:31
@ SEC_RW_NS_R
Definition: devapc.h:34
@ SEC_RW_ONLY
Definition: devapc.h:33
@ FORBIDDEN
Definition: devapc.h:35
@ NO_PROTECTION
Definition: devapc.h:32
@ DOM_NUM_INFRA_AO_SYS0
Definition: devapc.h:71
#define MOD_NO_IN_1_DEVAPC
Definition: devapc.h:86
@ SYS0_D0_APC_0
Definition: devapc.h:14
@ AO_APC_CON
Definition: devapc.h:19
@ MAS_DOM_0
Definition: devapc.h:17
@ DOM_REMAP_0_0
Definition: devapc.h:15
@ MAS_SEC_0
Definition: devapc.h:18
domain_id
Definition: devapc.h:39
@ DOMAIN_0
Definition: devapc.h:40
@ DOMAIN_3
Definition: devapc.h:43
@ DOMAIN_1
Definition: devapc.h:41
@ DOMAIN_5
Definition: devapc.h:45
@ DOMAIN_7
Definition: devapc.h:47
@ DOMAIN_15
Definition: devapc.h:55
@ DOMAIN_2
Definition: devapc.h:42
@ DOMAIN_6
Definition: devapc.h:46
@ DOMAIN_14
Definition: devapc.h:54
@ DOMAIN_11
Definition: devapc.h:51
@ DOMAIN_12
Definition: devapc.h:52
@ DOMAIN_9
Definition: devapc.h:49
@ DOMAIN_8
Definition: devapc.h:48
@ DOMAIN_10
Definition: devapc.h:50
@ DOMAIN_13
Definition: devapc.h:53
@ DOMAIN_4
Definition: devapc.h:44
@ ADSP_DOM
Definition: devapc.h:26
@ SCP_DOM
Definition: devapc.h:25
@ ONETIME_LOCK
Definition: devapc.h:27
@ DOM_REMAP_2_0
Definition: devapc.h:17
static void set_peri_ao_apc(uintptr_t base)
Definition: devapc.c:1691
static void dump_peri2_ao_apc(uintptr_t base)
Definition: devapc.c:1784
static void dump_peri_ao_apc(uintptr_t base)
Definition: devapc.c:1763
static void dump_scp_master(uintptr_t base)
Definition: devapc.c:1823
static void set_infra_ao_apc(uintptr_t base)
Definition: devapc.c:1671
static void infra2_init(uintptr_t base)
Definition: devapc.c:1943
static void peri_init(uintptr_t base)
Definition: devapc.c:1875
static void * getreg(uintptr_t base, unsigned int offset)
Definition: devapc.c:1652
static void infra_init(uintptr_t base)
Definition: devapc.c:1831
static void set_module_apc(uintptr_t base, uint32_t module, enum domain_id domain_id, enum devapc_perm_type perm)
Definition: devapc.c:1657
static void set_peri_par_ao_apc(uintptr_t base)
Definition: devapc.c:1723
static void * getreg_domain(uintptr_t base, unsigned int offset, enum domain_id domain_id, unsigned int index)
Definition: devapc.c:1646
static const struct apc_infra_peri_dom_4 infra_ao_sys2_devices[]
Definition: devapc.c:716
static void scp_master_init(uintptr_t base)
Definition: devapc.c:1956
static void peri_par_init(uintptr_t base)
Definition: devapc.c:1904
static void dump_infra_ao_apc(uintptr_t base)
Definition: devapc.c:1733
static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[]
Definition: devapc.c:8
static void peri2_init(uintptr_t base)
Definition: devapc.c:1898
static const struct apc_infra_peri_dom_4 infra_ao_sys1_devices[]
Definition: devapc.c:175
static void dump_fmem_ao(uintptr_t base)
Definition: devapc.c:1811
static const struct apc_infra_peri_dom_8 peri_ao_sys1_devices[]
Definition: devapc.c:1231
static const struct apc_infra_peri_dom_16 peri_par_ao_sys0_devices[]
Definition: devapc.c:1543
static enum domain_id domain_map[]
Definition: devapc.c:1641
static void fmem_master_init(uintptr_t base)
Definition: devapc.c:1924
static void dump_infra2_ao_apc(uintptr_t base)
Definition: devapc.c:1817
static void dump_peri_par_ao_apc(uintptr_t base)
Definition: devapc.c:1796
static const struct apc_infra_peri_dom_16 peri_ao_sys0_devices[]
Definition: devapc.c:1095
static void set_peri2_ao_apc(uintptr_t base)
Definition: devapc.c:1713
static const struct apc_infra_peri_dom_16 peri2_ao_sys0_devices[]
Definition: devapc.c:1283
#define DAPC_INFRA_AO_SYS2_ATTR(...)
Definition: devapc.h:96
#define DAPC_PERI2_AO_SYS0_ATTR(...)
Definition: devapc.h:99
#define DAPC_PERI_PAR_AO_SYS0_ATTR(...)
Definition: devapc.h:100
#define DAPC_PERI_AO_SYS1_ATTR(...)
Definition: devapc.h:98
#define DAPC_PERI_AO_SYS0_ATTR(...)
Definition: devapc.h:97
@ DOM_NUM_PERI2_AO_SYS0
Definition: devapc.h:85
@ DOM_NUM_INFRA_AO_SYS1
Definition: devapc.h:81
@ DOM_NUM_INFRA_AO_SYS2
Definition: devapc.h:82
@ DOM_NUM_PERI_AO_SYS1
Definition: devapc.h:84
@ DOM_NUM_PERI_AO_SYS0
Definition: devapc.h:83
@ DOM_NUM_PERI_PAR_AO_SYS0
Definition: devapc.h:86
@ SYS1_D0_APC_0
Definition: devapc.h:13
@ MAS_DOM_4
Definition: devapc.h:20
@ SYS2_D0_APC_0
Definition: devapc.h:14
#define DAPC_INFRA_AO_SYS1_ATTR(...)
Definition: devapc.h:95
uintptr_t base
Definition: uart.c:17
@ DEVAPC_FMEM_AO_BASE
Definition: addressmap.h:38
@ DEVAPC_INFRA_AO_BASE
Definition: addressmap.h:34
@ SCP_CFG_BASE
Definition: addressmap.h:48
@ DEVAPC_PERI_AO_BASE
Definition: addressmap.h:35
@ DEVAPC_PERI2_AO_BASE
Definition: addressmap.h:36
@ DEVAPC_PERI_PAR_AO_BASE
Definition: addressmap.h:37
@ DEVAPC_INFRA2_AO_BASE
Definition: addressmap.h:46
int dump
Definition: display.c:23
unsigned int uint32_t
Definition: stdint.h:14
unsigned long uintptr_t
Definition: stdint.h:21
unsigned char d_permission[16]
Definition: devapc.h:59
uintptr_t base
Definition: devapc.c:1298
void(* init)(uintptr_t base)
Definition: devapc.c:1299
void(* dump)(uintptr_t base)
Definition: devapc.c:1300
uintptr_t base
Definition: devapc.c:113
void(* init)(uintptr_t base)
Definition: devapc.c:114
typedef void(X86APIP X86EMU_intrFuncs)(int num)