coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
oxpcie_early.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <stdint.h>
4 #include <stddef.h>
5 #include <device/pci_ops.h>
6 #include <console/uart.h>
7 #include <device/pci.h>
8 #include <device/pci_def.h>
9 
10 static unsigned int oxpcie_present;
11 static DEVTREE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
12 
13 int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
14 {
15  pci_devfn_t device = PCI_DEV(bus, dev, 0);
16 
18  switch (id) {
19  case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
20  /* On this device function 0 is the parallel port, and
21  * function 3 is the serial port. So let's go look for
22  * the UART.
23  */
24  device = PCI_DEV(bus, dev, 3);
26  if (id != 0xc11b1415)
27  return -1;
28  break;
29  case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */
30  case 0xc1581415: /* e.g. Startech MPEX2S952 */
31  break;
32  default:
33  /* No UART here. */
34  return -1;
35  }
36 
37  /* Sanity-check, we assume fixed location. */
38  if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE)
39  return -1;
40 
41  /* Setup base address on device */
43 
44  /* Enable memory on device */
46  reg16 |= PCI_COMMAND_MEMORY;
48 
49  oxpcie_present = 1;
50  return 0;
51 }
52 
53 static int oxpcie_uart_active(void)
54 {
55  return oxpcie_present;
56 }
57 
58 uintptr_t uart_platform_base(unsigned int idx)
59 {
60  if ((idx < 8) && oxpcie_uart_active())
61  return uart0_base + idx * 0x200;
62  return 0;
63 }
64 
65 void oxford_remap(u32 new_base)
66 {
67 #if ENV_RAMSTAGE
68  uart0_base = new_base + 0x1000;
69 #endif
70 }
71 
72 unsigned int uart_platform_refclk(void)
73 {
74  return 62500000;
75 }
void oxford_remap(u32 new_base)
Definition: oxpcie_early.c:65
static int oxpcie_uart_active(void)
Definition: oxpcie_early.c:53
int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
Definition: oxpcie_early.c:13
uintptr_t uart_platform_base(unsigned int idx)
Definition: oxpcie_early.c:58
unsigned int uart_platform_refclk(void)
Definition: oxpcie_early.c:72
static DEVTREE_CONST u32 uart0_base
Definition: oxpcie_early.c:11
static unsigned int oxpcie_present
Definition: oxpcie_early.c:10
#define PCI_COMMAND_MEMORY
Definition: pci_def.h:12
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
#define PCI_COMMAND
Definition: pci_def.h:10
#define PCI_VENDOR_ID
Definition: pci_def.h:8
static __always_inline uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
Definition: pci_io_cfg.h:92
static __always_inline uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg)
Definition: pci_io_cfg.h:86
static __always_inline void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
Definition: pci_io_cfg.h:104
static __always_inline void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
Definition: pci_io_cfg.h:110
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
u32 pci_devfn_t
Definition: pci_type.h:8
#define DEVTREE_CONST
Definition: stddef.h:30
uint32_t u32
Definition: stdint.h:51
unsigned long uintptr_t
Definition: stdint.h:21
uint16_t u16
Definition: stdint.h:48
uint8_t u8
Definition: stdint.h:45
Definition: device.h:76
Definition: device.h:107