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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <stdint.h>
Go to the source code of this file.
Macros | |
#define | __CONSOLE_SERIAL_ENABLE__ |
#define __CONSOLE_SERIAL_ENABLE__ |
Definition at line 82 of file uart.h.
Referenced by console_hw_init().
Definition at line 83 of file uart.h.
Referenced by console_interactive_tx_byte(), print_exception_info(), and vprintk().
Definition at line 84 of file uart.h.
Referenced by console_tx_flush().
Definition at line 65 of file oxpcie_early.c.
References uart0_base.
unsigned int uart_baudrate_divisor | ( | unsigned int | baudrate, |
unsigned int | refclk, | ||
unsigned int | oversample | ||
) |
Definition at line 8 of file util.c.
Referenced by uart_init().
Definition at line 48 of file util.c.
References get_uart_baudrate(), MHz, set_tx(), stopwatch_duration_usecs(), stopwatch_init(), and stopwatch_tick().
Referenced by uart_tx_byte().
ipq40xx_uart_init - initializes UART
Initializes clocks, GPIO and UART controller.
ipq40xx_uart_init - initializes UART
Initializes clocks, GPIO and UART controller.
Definition at line 8 of file pl011.c.
References am335x_uart_init(), assert, base, uart_params_t::blsp_uart, clock_configure_uart(), clock_enable_qup(), clock_enable_uart(), CONFIG, uart_clk_mnd_t::d_value, uart_params_t::dbg_uart_gpio, DIV_ROUND_CLOSEST, exynos5_init_dev(), FIFO, FIFO_DEPTH, GENI_FW_REVISION_RO_PROTOCOL_MASK, GENI_FW_REVISION_RO_PROTOCOL_SHIFT, GENI_STATUS_S_GENI_CMD_ACTIVE_MASK, get_uart_baudrate(), GPIO_2MA, gpio_configure(), GPIO_INPUT, gpio_output(), GPIO_OUTPUT, GPIO_PULL_UP, GSBI_CTRL_REG, GSBI_CTRL_REG_PROTOCOL_CODE_S, GSBI_PROTOCOL_CODE_I2C_UART, ipq_configure_gpio(), uart_clk_mnd_t::m_value, uart_params_t::mnd_value, MSM_BOOT_UART_DM_CSR, msm_boot_uart_dm_init(), mtk_uart_init(), uart_clk_mnd_t::n_value, NO_OF_DBG_UART_GPIOS, qupv3_se_fw_load_and_init(), read32(), qup::regs, SE_PROTOCOL_UART, sifive_uart_init(), SRC_XO_HZ, START_UART_RX, tegra124_uart_init(), tegra210_uart_init(), uart8250_init(), uart8250_mem_init(), uart_baudrate_divisor(), uart_board_param, uart_clock_config(), uart_params_t::uart_dm_base, UART_DM_CLK_RX_TX_BIT_RATE, uart_params_t::uart_gsbi, uart_params_t::uart_gsbi_base, uart_input_clock_divider(), uart_platform_base(), uart_platform_baseptr(), uart_platform_refclk(), uart_ptr, UART_RX_BITS_PER_WORD, UART_RX_PACK_VECTOR0, UART_RX_PACK_VECTOR2, UART_RX_RFR_WATERMARK_MARGIN, UART_RX_WATERMARK_MARGIN, UART_TX_BITS_PER_WORD, UART_TX_PACK_VECTOR0, UART_TX_PACK_VECTOR1, UART_TX_PACK_VECTOR2, UART_TX_PACK_VECTOR3, UART_TX_PIN, UART_TX_WATERMARK_MARGIN, and write32().
Referenced by ipq40xx_uart_init(), ipq806x_uart_init(), main(), and qcs405_uart_init().
Definition at line 94 of file sifive.c.
Referenced by uart_init().
Definition at line 58 of file oxpcie_early.c.
References ARRAY_SIZE, base, bases, buf, FU540_UART, get_uart_base(), MY_PCI_DEV, oxpcie_uart_active(), PCI_BASE_ADDRESS_1, pci_io_read_config32(), QEMU_VIRT_UART0, qup::regs, SIZE_OF_HSUART_RES, uart0_base, UART_BASE_ADDRESS, VEXPRESS_UART0_IO_ADDRESS, and VIRT_UART_BASE.
Referenced by platform_fsp_memory_init_params_cb(), uart_fill_lb(), uart_init(), uart_platform_baseptr(), uart_rx_byte(), uart_tx_byte(), and uart_tx_flush().
Definition at line 57 of file uart.h.
References uart_platform_base().
Referenced by uart_init(), uart_rx_byte(), uart_tx_byte(), and uart_tx_flush().
Definition at line 72 of file oxpcie_early.c.
References clock_get_tlclk_khz(), KHz, OSC_HZ, and uart_hclk().
Referenced by dt_platform_fixup(), platform_fsp_memory_init_params_cb(), uart_fill_lb(), and uart_init().
ipq40xx_serial_getc - reads a character
Returns the character read from serial port.
ipq40xx_serial_getc - reads a character
Returns 1 if data available, 0 otherwise ipq806x_serial_getc - reads a character
Returns the character read from serial port.
Definition at line 29 of file pl011.c.
References am335x_uart_rx_byte(), base, exynos5_uart_rx_byte(), mtk_uart_rx_byte(), PL011_UARTFR_RXFE, read32(), read8(), qup::regs, RX_FIFO_WC_MSK, sifive_uart_registers::rxdata, RXDATA_EMPTY, tegra124_uart_rx_byte(), tegra210_uart_rx_byte(), uart8250_mem_rx_byte(), uart8250_rx_byte(), uart_platform_base(), uart_platform_baseptr(), uart_ptr, valid_data, and word.
msm_boot_uart_dm_read - reads a word from the RX FIFO.
@data: location where the read data is stored @count: no of valid data in the FIFO @wait: indicates blocking call or not blocking call
Reads a word from the RX FIFO. If no data is available blocks if @wait is true, else returns MSM_BOOT_UART_DM_E_RX_NOT_READY.
Definition at line 12 of file pl011.c.
References am335x_uart_tx_byte(), base, exynos5_uart_tx_byte(), MSM_BOOT_UART_DM_NO_CHARS_FOR_TX, MSM_BOOT_UART_DM_SR, MSM_BOOT_UART_DM_SR_TXEMT, MSM_BOOT_UART_DM_TF, mtk_uart_tx_byte(), read32(), qup::regs, set_tx(), START_UART_TX, tegra124_uart_tx_byte(), tegra210_uart_tx_byte(), uart8250_mem_tx_byte(), uart8250_tx_byte(), uart_bitbang_tx_byte(), uart_board_param, uart_can_tx(), uart_params_t::uart_dm_base, uart_platform_base(), uart_platform_baseptr(), uart_ptr, uart_tx_flush(), udelay(), write32(), and write8().
uart_tx_flush - transmits a string of data
idx | string to transmit |
uart_tx_flush - transmits a string of data
Definition at line 20 of file pl011.c.
References base, exynos5_uart_tx_flush(), GENI_STATUS_M_GENI_CMD_ACTIVE_MASK, sifive_uart_registers::ip, IP_TXWM, MSM_BOOT_UART_DM_SR, MSM_BOOT_UART_DM_SR_TXEMT, mtk_uart_tx_flush(), PL011_UARTFR_TXFE, read32(), qup::regs, tegra124_uart_tx_flush(), tegra210_uart_tx_flush(), uart8250_mem_tx_flush(), uart8250_tx_flush(), uart_board_param, uart_params_t::uart_dm_base, uart_platform_base(), uart_platform_baseptr(), and uart_ptr.
Referenced by uart_tx_byte().