romstage.c

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/* SPDX-License-Identifier: GPL-2.0-only */
 
#include <arch/romstage.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/cfg.h>
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/smbus.h>
#include <memory_info.h>
#include <soc/intel/common/smbios.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <string.h>
 
#include "../chip.h"
 
#define FSP_SMBIOS_MEMORY_INFO_GUID     \
{       \
        0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
        0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23  \
}
 
/* Save the DIMM information for SMBIOS table 17 */
static void save_dimm_info(void)
{
        int channel, dimm, dimm_max, index;
        size_t hob_size;
        const CONTROLLER_INFO *ctrlr_info;
        const CHANNEL_INFO *channel_info;
        const DIMM_INFO *src_dimm;
        struct dimm_info *dest_dimm;
        struct memory_info *mem_info;
        const MEMORY_INFO_DATA_HOB *memory_info_hob;
        const uint8_t smbios_memory_info_guid[16] =
                        FSP_SMBIOS_MEMORY_INFO_GUID;
        const char *dram_part_num;
        size_t dram_part_num_len = 0;
        bool part_num_overridden = false;
 
        /* Locate the memory info HOB, presence validated by raminit */
        memory_info_hob = fsp_find_extension_hob_by_guid(
                                                smbios_memory_info_guid,
                                                &hob_size);
        if (memory_info_hob == NULL || hob_size == 0) {
                printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
                return;
        }
 
        /*
         * Allocate CBMEM area for DIMM information used to populate SMBIOS
         * table 17
         */
        mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
        if (mem_info == NULL) {
                printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
                return;
        }
        memset(mem_info, 0, sizeof(*mem_info));
 
        /* Allow mainboard to override DRAM part number. */
        dram_part_num = mainboard_get_dram_part_num();
        if (dram_part_num) {
                dram_part_num_len = strlen(dram_part_num);
                part_num_overridden = true;
        }
 
        /* Describe the first N DIMMs in the system */
        index = 0;
        dimm_max = ARRAY_SIZE(mem_info->dimm);
        ctrlr_info = &memory_info_hob->Controller[0];
        for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
                channel_info = &ctrlr_info->ChannelInfo[channel];
                if (channel_info->Status != CHANNEL_PRESENT)
                        continue;
                for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
                        src_dimm = &channel_info->DimmInfo[dimm];
                        dest_dimm = &mem_info->dimm[index];
 
                        if (src_dimm->Status != DIMM_PRESENT)
                                continue;
 
                        if (!part_num_overridden) {
                                dram_part_num_len =
                                                sizeof(src_dimm->ModulePartNum);
                                dram_part_num = (const char *)
                                                &src_dimm->ModulePartNum[0];
                        }
 
                        u8 memProfNum = memory_info_hob->MemoryProfile;
 
                        /* Populate the DIMM information */
                        dimm_info_fill(dest_dimm,
                                src_dimm->DimmCapacity,
                                memory_info_hob->MemoryType,
                                memory_info_hob->ConfiguredMemoryClockSpeed,
                                src_dimm->RankInDimm,
                                channel_info->ChannelId,
                                src_dimm->DimmId,
                                dram_part_num,
                                dram_part_num_len,
                                src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL,
                                memory_info_hob->DataWidth,
                                memory_info_hob->VddVoltage[memProfNum],
                                memory_info_hob->EccSupport,
                                src_dimm->MfgId,
                                src_dimm->SpdModuleType);
                        index++;
                }
        }
        mem_info->dimm_cnt = index;
        printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
 
void mainboard_romstage_entry(void)
{
        bool s3wake;
        struct chipset_power_state *ps = pmc_get_power_state();
 
        /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
        systemagent_early_init();
        /* Program SMBus base address and enable it */
        smbus_common_init();
        /* initialize Heci interface */
        heci_init(HECI1_BASE_ADDRESS);
 
        s3wake = pmc_fill_power_state(ps) == ACPI_S3;
        fsp_memory_init(s3wake);
        pmc_set_disb();
        if (!s3wake) {
                /*
                 * cse_fw_sync() must be called after DRAM initialization as
                 * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())
                 * is expected to be executed after DRAM initialization.
                 */
 
                if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
                        cse_fw_sync();
 
                save_dimm_info();
        }
}