15 #include <soc/pci_devs.h>
16 #include <soc/soc_chip.h>
void configure_dca_cap(void)
void set_energy_perf_bias(u8 policy)
void enable_lapic_tpr(void)
#define MSR_C_STATE_LATENCY_CONTROL_1
#define C_STATE_LATENCY_CONTROL_4_LIMIT
#define C_STATE_LATENCY_CONTROL_2_LIMIT
#define C_STATE_LATENCY_CONTROL_3_LIMIT
#define C_STATE_LATENCY_CONTROL_1_LIMIT
#define MSR_C_STATE_LATENCY_CONTROL_5
#define C_STATE_LATENCY_CONTROL_5_LIMIT
#define MSR_C_STATE_LATENCY_CONTROL_2
#define MSR_C_STATE_LATENCY_CONTROL_3
#define MSR_C_STATE_LATENCY_CONTROL_4
void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase)
void smm_initialize(void)
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size)
enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops)
void cpu_set_eist(bool eist_status)
void cpu_set_max_ratio(void)
static __always_inline msr_t rdmsr(unsigned int index)
#define IA32_PACKAGE_THERM_INTERRUPT
#define ENERGY_POLICY_NORMAL
static __always_inline void wrmsr(unsigned int index, msr_t msr)
#define IA32_THERM_INTERRUPT
void global_smi_enable(void)
Set the EOS bit and enable SMI generation from southbridge.
void enable_pm_timer_emulation(void)
void soc_init_cpus(struct bus *cpu_bus)
bool cpu_soc_is_in_untrusted_mode(void)
void soc_core_init(struct device *cpu)
#define ENABLE_IA_UNTRUSTED
void get_microcode_info(const void **microcode, int *parallel)
static void configure_c_states(void)
static void configure_misc(void)
static void soc_fsp_load(void)
static void per_cpu_smm_trigger(void)
static void post_mp_init(void)
void(* pre_mp_init)(void)