coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
xhci.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <device/mmio.h>
5 #include <intelblocks/xhci.h>
6 #include <soc/soc_chip.h>
7 
8 #define XHCI_USB2_PORT_STATUS_REG 0x480
9 #define XHCI_USB3_PORT_STATUS_REG 0x500
10 #define XHCI_USB2_PORT_NUM 8
11 #define XHCI_USB3_PORT_NUM 6
12 
13 #define XHCI_PMCTRL 0x80A4
14 /* BIT[7:4] LFPS periodic sampling off time for USB3 Ports */
15 #define PMCTRL_LFPS_OFFTIME_SHIFT 4
16 #define PMCTRL_LFPS_OFFTIME_MAX 0xF
17 
18 static const struct xhci_usb_info usb_info = {
20  .num_usb2_ports = XHCI_USB2_PORT_NUM,
21  .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG,
22  .num_usb3_ports = XHCI_USB3_PORT_NUM,
23 };
24 
26 {
27  /* Jasper Lake only has one XHCI controller */
28  return &usb_info;
29 }
30 
31 static void set_xhci_lfps_sampling_offtime(struct device *dev, uint8_t time_ms)
32 {
33  void *addr;
34  const struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
35 
36  if (!res)
37  return;
38 
39  if (time_ms > PMCTRL_LFPS_OFFTIME_MAX) {
41  "XHCI: The maximum LFPS sampling OFF time is %u ms, "
42  "cannot set it to %u ms\n",
43  PMCTRL_LFPS_OFFTIME_MAX, time_ms);
44 
45  return;
46  }
47 
48  addr = (void *)(uintptr_t)(res->base + XHCI_PMCTRL);
51  time_ms << PMCTRL_LFPS_OFFTIME_SHIFT);
53  "XHCI: Updated LFPS sampling OFF time to %u ms\n", time_ms);
54 }
55 
56 void soc_xhci_init(struct device *dev)
57 {
58  const config_t *config = config_of_soc();
59 
60  /* Set xHCI LFPS period sampling off time */
62  config->xhci_lfps_sampling_offtime_ms);
63 }
static u32 addr
Definition: cirrus.c:14
#define printk(level,...)
Definition: stdlib.h:16
struct resource * probe_resource(const struct device *dev, unsigned int index)
See if a resource structure already exists for a given index.
Definition: device_util.c:323
#define config_of_soc()
Definition: device.h:394
#define clrsetbits32(addr, clear, set)
Definition: mmio.h:16
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
Definition: loglevel.h:72
enum board_config config
Definition: memory.c:448
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
u32 pci_devfn_t
Definition: pci_type.h:8
const struct xhci_usb_info * soc_get_xhci_usb_info(pci_devfn_t xhci_dev)
Definition: xhci.c:36
#define XHCI_USB3_PORT_STATUS_REG
Definition: xhci.c:9
static const struct xhci_usb_info usb_info
Definition: xhci.c:18
#define XHCI_USB3_PORT_NUM
Definition: xhci.c:11
#define PMCTRL_LFPS_OFFTIME_MAX
Definition: xhci.c:16
#define PMCTRL_LFPS_OFFTIME_SHIFT
Definition: xhci.c:15
#define XHCI_USB2_PORT_NUM
Definition: xhci.c:10
#define XHCI_PMCTRL
Definition: xhci.c:13
void soc_xhci_init(struct device *dev)
Definition: xhci.c:56
#define XHCI_USB2_PORT_STATUS_REG
Definition: xhci.c:8
static void set_xhci_lfps_sampling_offtime(struct device *dev, uint8_t time_ms)
Definition: xhci.c:31
unsigned long uintptr_t
Definition: stdint.h:21
unsigned char uint8_t
Definition: stdint.h:8
Definition: device.h:107
resource_t base
Definition: resource.h:45
uint32_t usb2_port_status_reg
Definition: xhci.h:18