coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
fsp_params.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <assert.h>
4 #include <console/console.h>
5 #include <fsp/util.h>
6 #include <intelblocks/cpulib.h>
7 #include <soc/iomap.h>
8 #include <soc/pci_devs.h>
9 #include <soc/romstage.h>
10 #include <soc/soc_chip.h>
11 
13  const struct soc_intel_icelake_config *config)
14 {
15  unsigned int i;
16  uint32_t mask = 0;
17 
18  /*
19  * If IGD is enabled, set IGD stolen size to 60MB.
20  * Otherwise, skip IGD init in FSP.
21  */
22  m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
23  m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
24 
25  m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
26  m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
27  m_cfg->SaGv = config->SaGv;
28  m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
29  m_cfg->RMT = config->RMT;
30  m_cfg->SkipMbpHob = 1;
31 
32  /* If Audio Codec is enabled, enable FSP UPD */
33  m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
34 
35  for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
36  if (config->PcieRpEnable[i])
37  mask |= (1 << i);
38  }
39  m_cfg->PcieRpEnableMask = mask;
40  m_cfg->PrmrrSize = get_valid_prmrr_size();
41  m_cfg->EnableC6Dram = config->enable_c6dram;
42  /* Disable BIOS Guard */
43  m_cfg->BiosGuard = 0;
44  /* Disable Cpu Ratio Override temporary. */
45  m_cfg->CpuRatio = 0;
46  m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
47  m_cfg->PcdDebugInterfaceFlags =
48  CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10;
49 
50  /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
51  m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
52 }
53 
55 {
56  const struct soc_intel_icelake_config *config;
57  FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
58 
60 
62 
63  /* Enable SMBus controller based on config */
64  m_cfg->SmbusEnable = config->SmbusEnable;
65  /* Set debug probe type */
66  m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ICELAKE_DEBUG_CONSENT;
67 
68  /* Vt-D config */
69  m_cfg->VtdDisable = 0;
70 
72 }
73 
75 {
76  printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
77 }
__weak void mainboard_memory_init_params(FSPM_UPD *memupd)
Definition: fsp_params.c:389
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
Definition: fsp_params.c:361
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
int get_valid_prmrr_size(void)
Definition: cpulib.c:397
bool is_devfn_enabled(unsigned int devfn)
Definition: device_const.c:382
@ CONFIG
Definition: dsi_common.h:201
#define FSP_M_CONFIG
Definition: fsp_upd.h:8
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_icelake_config *config)
Definition: fsp_params.c:12
#define config_of_soc()
Definition: device.h:394
unsigned int version[2]
Definition: edid.c:55
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
enum board_config config
Definition: memory.c:448
const struct smm_save_state_ops *legacy_ops __weak
Definition: save_state.c:8
#define PCH_DEVFN_HDA
Definition: pci_devs.h:218
#define SA_DEVFN_IGD
Definition: pci_devs.h:32
@ BOARD_TYPE_ULT_ULX
Definition: romstage.h:16
static const int mask[4]
Definition: gpio.c:308
unsigned int uint32_t
Definition: stdint.h:14