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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/hpet.h>
#include <bootblock_common.h>
#include <device/pnp_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
#include <superio/nuvoton/nct6779d/nct6779d.h>
#include <option.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/pei_data.h>
Go to the source code of this file.
Macros | |
#define | GLOBAL_DEV PNP_DEV(0x2e, 0) |
#define | SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) |
Functions | |
void | bootblock_mainboard_early_init (void) |
void | mainboard_get_spd (spd_raw_data *spd, bool id_only) |
int | mainboard_should_reset_usb (int s3resume) |
void | mainboard_fill_pei_data (struct pei_data *pei_data) |
Variables | |
const struct southbridge_usb_port | mainboard_usb_ports [] |
#define GLOBAL_DEV PNP_DEV(0x2e, 0) |
Definition at line 18 of file early_init.c.
#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) |
Definition at line 19 of file early_init.c.
Definition at line 39 of file early_init.c.
References GLOBAL_DEV, nuvoton_enable_serial(), nuvoton_pnp_enter_conf_state(), nuvoton_pnp_exit_conf_state(), pnp_set_logical_device(), and SERIAL_DEV.
Definition at line 64 of file early_init.c.
References DEFAULT_GPIOBASE, DEFAULT_PMBASE, DEFAULT_RCBA, get_uint_option(), pei_data::gpiobase, HPET_BASE_ADDRESS, PEI_VERSION, pei_data::pei_version, pmbase, pei_data::spd_addresses, pei_data::system_type, pei_data::thermalbase, and pei_data::tseg_size.
void mainboard_get_spd | ( | spd_raw_data * | spd, |
bool | id_only | ||
) |
Definition at line 51 of file early_init.c.
References read_spd().
int mainboard_should_reset_usb | ( | int | s3resume | ) |
Definition at line 59 of file early_init.c.
const struct southbridge_usb_port mainboard_usb_ports[] |
Definition at line 1 of file early_init.c.