coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_thermal.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <device/mmio.h>
4 #include <device/pci_ops.h>
5 #include "pch.h"
7 #include <cpu/x86/msr.h>
8 
9 /* Early thermal init, must be done prior to giving ME its memory
10  which is done at the end of raminit. */
12 {
13  pci_devfn_t dev;
14  msr_t msr;
15 
16  dev = PCI_DEV(0x0, 0x1f, 0x6);
17 
18  /* Program address for temporary BAR. */
19  pci_write_config32(dev, 0x40, 0x40000000);
20  pci_write_config32(dev, 0x44, 0x0);
21 
22  /* Activate temporary BAR. */
23  pci_write_config32(dev, 0x40,
24  pci_read_config32(dev, 0x40) | 5);
25 
26  /* Perform init. */
27  /* Configure TJmax. */
29  write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
30  /* Northbridge temperature slope and offset. */
31  write16((u16 *)0x40000016, 0x7746);
32  /* Enable thermal data reporting, processor, PCH and northbridge. */
33  write16((u16 *)0x4000001a,
34  (read16((u16 *)0x4000001a) & ~0xf) | 0x10f0);
35 
36  /* Disable temporary BAR. */
37  pci_write_config32(dev, 0x40,
38  pci_read_config32(dev, 0x40) & ~1);
39  pci_write_config32(dev, 0x40, 0);
40 }
static uint16_t read16(const void *addr)
Definition: mmio.h:17
static void write16(void *addr, uint16_t val)
Definition: mmio.h:35
void early_thermal_init(void)
Definition: early_thermal.c:14
#define MSR_TEMPERATURE_TARGET
Definition: haswell.h:50
static __always_inline msr_t rdmsr(unsigned int index)
Definition: msr.h:146
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
u32 pci_devfn_t
Definition: pci_type.h:8
uint16_t u16
Definition: stdint.h:48
unsigned int lo
Definition: msr.h:111