coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
sata.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ops.h>
6 #include <device/pci_def.h>
7 #include <amdblocks/sata.h>
8 #include <soc/southbridge.h>
9 
11 {
12  u8 *ahci_ptr;
13  u32 misc_ctl, cap_cfg;
14 
15  u32 temp;
16 
17  /* unlock the write-protect */
19  misc_ctl |= SATA_MISC_SUBCLASS_WREN;
21 
22  /* set the SATA AHCI mode to allow port expanders */
23  ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN(
25 
26  cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG);
27  cap_cfg |= SATA_CAPABILITY_SPM;
28  write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg);
29 
30  /* lock the write-protect */
32  temp &= ~SATA_MISC_SUBCLASS_WREN;
34 };
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
static uint32_t read32(const void *addr)
Definition: mmio.h:22
#define ALIGN_DOWN(x, a)
Definition: helpers.h:18
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
#define PCI_BASE_ADDRESS_5
Definition: pci_def.h:68
#define SATA_MISC_SUBCLASS_WREN
Definition: southbridge.h:100
#define SATA_CAPABILITY_SPM
Definition: southbridge.h:103
#define SATA_MISC_CONTROL_REG
Definition: southbridge.h:99
#define SATA_CAPABILITIES_REG
Definition: southbridge.h:102
void soc_enable_sata_features(struct device *dev)
Definition: sata.c:10
uint32_t u32
Definition: stdint.h:51
unsigned long uintptr_t
Definition: stdint.h:21
uint8_t u8
Definition: stdint.h:45
Definition: device.h:107