8 #include <soc/southbridge.h>
13 u32 misc_ctl, cap_cfg;
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
#define PCI_BASE_ADDRESS_5
#define SATA_MISC_SUBCLASS_WREN
#define SATA_CAPABILITY_SPM
#define SATA_MISC_CONTROL_REG
#define SATA_CAPABILITIES_REG
void soc_enable_sata_features(struct device *dev)