coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
device/pci_ops.h
>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <
superio/ite/common/ite.h
>
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#include <
superio/ite/it8613e/it8613e.h
>
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#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1)
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void
mainboard_after_memory_init
(
void
)
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{
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/*
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* FSP enables internal UART. Disable it and re-enable Super I/O UART to
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* prevent loss of debug information on serial.
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*/
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pci_write_config32
(
PCI_DEV
(0,
LPC_DEV
, 0),
UART_CONT
, (
u32
) 0);
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ite_enable_serial
(
SERIAL1_DEV
, CONFIG_TTYS0_BASE);
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}
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void
mainboard_memory_init_params
(
struct
romstage_params
*
params
,
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MEMORY_INIT_UPD *
memory_params
)
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{
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/*
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* Set SPD and memory configuration:
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* Memory type: 0=DimmInstalled,
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* 1=SolderDownMemory,
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* 2=DimmDisabled
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*/
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memory_params
->PcdMemChannel0Config = 0;
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memory_params
->PcdMemChannel1Config = 2;
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}
params
static struct sdram_info params
Definition:
sdram_configs.c:83
pci_ops.h
pci_write_config32
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition:
pci_ops.h:76
it8613e.h
ite_enable_serial
void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition:
early_serial.c:61
ite.h
mainboard_memory_init_params
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition:
romstage.c:22
mainboard_after_memory_init
void mainboard_after_memory_init(void)
Definition:
romstage.c:49
SERIAL1_DEV
#define SERIAL1_DEV
Definition:
romstage.c:10
LPC_DEV
#define LPC_DEV
Definition:
romstage.c:15
PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN)
Definition:
pci_type.h:14
UART_CONT
#define UART_CONT
Definition:
lpc.h:16
u32
uint32_t u32
Definition:
stdint.h:51
memory_params
Definition:
variants.h:31
romstage_params
Definition:
romstage.h:13
src
mainboard
protectli
vault_bsw
romstage.c
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