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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include "iobp.h"
#include "pch.h"
Go to the source code of this file.
Functions | |
static struct device * | pch_get_lpc_device (void) |
int | pch_silicon_revision (void) |
int | pch_silicon_id (void) |
enum pch_platform_type | get_pch_platform_type (void) |
u16 | get_pmbase (void) |
u16 | get_gpiobase (void) |
static void | pch_enable_d3hot (struct device *dev) |
void | pch_disable_devfn (struct device *dev) |
void | pch_enable (struct device *dev) |
Variables | |
struct chip_operations | southbridge_intel_lynxpoint_ops |
Definition at line 69 of file pch.c.
References GPIOBASE, pch_get_lpc_device(), and pci_read_config16().
enum pch_platform_type get_pch_platform_type | ( | void | ) |
Definition at line 33 of file pch.c.
References pch_get_lpc_device(), PCI_DEVICE_ID, and pci_read_config16().
Definition at line 59 of file pch.c.
References ACPI_BASE_ADDRESS, pch_get_lpc_device(), pci_read_config16(), PMBASE, and pmbase.
Referenced by acpi_fill_fadt(), add_simple_resources(), gma_enable_swsci(), pch_log_gpe(), pch_log_gpio_gpe(), pch_log_standard_gpe(), pch_log_state(), pch_lpc_add_io_resources(), pch_power_options(), and smm_southbridge_clear_state().
Definition at line 88 of file pch.c.
References BUC, pci_path::devfn, FD, FD2, device::path, PCH_DEV_SLOT_PCIE, PCH_DEVFN_ADSP, PCH_DEVFN_EHCI, PCH_DEVFN_GBE, PCH_DEVFN_HDA, PCH_DEVFN_I2C0, PCH_DEVFN_I2C1, PCH_DEVFN_LPC, PCH_DEVFN_ME, PCH_DEVFN_ME_2, PCH_DEVFN_ME_IDER, PCH_DEVFN_ME_KT, PCH_DEVFN_SATA, PCH_DEVFN_SATA2, PCH_DEVFN_SDIO, PCH_DEVFN_SDMA, PCH_DEVFN_SMBUS, PCH_DEVFN_SPI0, PCH_DEVFN_SPI1, PCH_DEVFN_THERMAL, PCH_DEVFN_UART0, PCH_DEVFN_UART1, PCH_DEVFN_XHCI, PCH_DISABLE_ADSPD, PCH_DISABLE_EHCI1, PCH_DISABLE_EHCI2, PCH_DISABLE_GBE, PCH_DISABLE_HD_AUDIO, PCH_DISABLE_IDER, PCH_DISABLE_KT, PCH_DISABLE_LPC, PCH_DISABLE_MEI1, PCH_DISABLE_MEI2, PCH_DISABLE_PCIE, PCH_DISABLE_SATA1, PCH_DISABLE_SATA2, PCH_DISABLE_SMBUS, PCH_DISABLE_THERMAL, PCH_DISABLE_XHCI, pch_enable_d3hot(), pch_iobp_update(), device_path::pci, PCI_DEVFN, PCI_FUNC, RCBA32_OR, rcba_function_disable(), SIO_IOBP_FUNCDIS0, SIO_IOBP_FUNCDIS1, SIO_IOBP_FUNCDIS2, SIO_IOBP_FUNCDIS3, SIO_IOBP_FUNCDIS4, SIO_IOBP_FUNCDIS5, SIO_IOBP_FUNCDIS6, SIO_IOBP_FUNCDIS7, and SIO_IOBP_FUNCDIS_DIS.
Referenced by ehci_enable(), hda_enable(), and root_port_commit_config().
Definition at line 181 of file pch.c.
References BIOS_DEBUG, dev_path(), pci_path::devfn, device::enabled, device::path, pch_disable_devfn(), PCH_PCIE_DEV_SLOT, device_path::pci, pci_and_config16(), PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, PCI_COMMAND_SERR, pci_or_config16(), PCI_SLOT, and printk.
Definition at line 82 of file pch.c.
References PCH_PCS, PCH_PCS_PS_D3HOT, and pci_or_config32().
Referenced by pch_disable_devfn().
Definition at line 17 of file pch.c.
References pcidev_on_root().
Referenced by get_gpiobase(), get_pch_platform_type(), get_pmbase(), and pch_silicon_revision().
int pch_silicon_id | ( | void | ) |
Definition at line 33 of file pch.c.
Referenced by max_root_ports().
int pch_silicon_revision | ( | void | ) |
Definition at line 23 of file pch.c.
References pch_get_lpc_device(), pci_read_config8(), and PCI_REVISION_ID.
struct chip_operations southbridge_intel_lynxpoint_ops |