coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_smbus.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/pci_def.h>
4 #include <device/pci_ids.h>
5 #include <device/pci_ops.h>
6 #include <device/smbus_host.h>
7 #include "early_smbus.h"
8 
10 {
11  return CONFIG_FIXED_SMBUS_IO_BASE;
12 }
13 
15 {
16  /* Set the SMBus device statically. */
17  const pci_devfn_t dev = PCI_DEV_SMBUS;
18 
19  /* Check to make sure we've got the right device. */
21  return -1;
22 
23  /* Set SMBus I/O base. */
25 
26  /* Set SMBus enable. */
28 
29  /* Set SMBus I/O space enable. */
31 
32  return 0;
33 }
int smbus_enable_iobar(uintptr_t base)
Definition: early_smbus.c:14
uintptr_t smbus_base(void)
Definition: early_smbus.c:9
#define PCI_DEV_SMBUS
Definition: early_smbus.h:8
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
Definition: pci_ops.h:52
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition: pci_ops.h:70
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val)
Definition: pci_ops.h:64
#define PCI_BASE_ADDRESS_SPACE_IO
Definition: pci_def.h:70
#define PCI_COMMAND_IO
Definition: pci_def.h:11
#define PCI_COMMAND
Definition: pci_def.h:10
#define PCI_VENDOR_ID
Definition: pci_def.h:8
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
u32 pci_devfn_t
Definition: pci_type.h:8
#define HST_EN
Definition: smbuslib.h:11
uintptr_t base
Definition: uart.c:17
#define HOSTC
Definition: smbus.h:7
#define SMB_BASE
Definition: smbus.h:7
unsigned long uintptr_t
Definition: stdint.h:21