coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
stdint.h
>
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#include <
southbridge/intel/ibexpeak/pch.h
>
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#include <
northbridge/intel/ironlake/ironlake.h
>
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/* Seems copied from Lenovo Thinkpad x201, might be wrong */
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const
struct
southbridge_usb_port
mainboard_usb_ports
[] = {
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/* Enabled, Current table lookup index, OC map */
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{ 1,
IF1_557
, 0 },
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{ 1,
IF1_55F
, 1 },
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{ 1,
IF1_74B
, 3 },
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{ 1,
IF1_74B
, 3 },
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{ 1,
IF1_557
, 3 },
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{ 1,
IF1_14B
, 3 },
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{ 1,
IF1_74B
, 3 },
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{ 1,
IF1_74B
, 3 },
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{ 1,
IF1_74B
, 4 },
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{ 1,
IF1_74B
, 5 },
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{ 1,
IF1_55F
, 7 },
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{ 1,
IF1_55F
, 7 },
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{ 1,
IF1_557
, 7 },
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{ 1,
IF1_55F
, 7 },
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};
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void
mainboard_pre_raminit
(
void
)
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{
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}
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void
mainboard_get_spd_map
(
u8
*spd_addrmap)
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{
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spd_addrmap[0] = 0x50;
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spd_addrmap[2] = 0x52;
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}
mainboard_pre_raminit
__weak void mainboard_pre_raminit(struct romstage_params *params)
Definition:
romstage.c:133
ironlake.h
mainboard_get_spd_map
void mainboard_get_spd_map(u8 *spd_addrmap)
Definition:
romstage.c:55
mainboard_usb_ports
const struct southbridge_usb_port mainboard_usb_ports[]
Definition:
romstage.c:9
pch.h
IF1_14B
@ IF1_14B
Definition:
pch.h:46
IF1_557
@ IF1_557
Definition:
pch.h:48
IF1_74B
@ IF1_74B
Definition:
pch.h:47
IF1_55F
@ IF1_55F
Definition:
pch.h:50
stdint.h
u8
uint8_t u8
Definition:
stdint.h:45
southbridge_usb_port
Definition:
pch.h:56
src
mainboard
packardbell
ms2290
romstage.c
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