coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Data Structures | Macros | Enumerations | Functions | Variables
pch.h File Reference
#include <acpi/acpi.h>
#include <southbridge/intel/common/rcba.h>
#include <device/device.h>
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Data Structures

struct  southbridge_usb_port
 

Macros

#define PCH_TYPE_CPT   0x1c /* CougarPoint */
 
#define PCH_TYPE_PPT   0x1e /* IvyBridge */
 
#define PCH_TYPE_MOBILE5   0x3b
 
#define PCH_STEP_A0   0
 
#define PCH_STEP_A1   1
 
#define PCH_STEP_B0   2
 
#define PCH_STEP_B1   3
 
#define PCH_STEP_B2   4
 
#define PCH_STEP_B3   5
 
#define SMBUS_SLAVE_ADDR   0x24
 
#define DEFAULT_GPIOBASE   0x0480
 
#define DEFAULT_PMBASE   0x0500
 
#define DEFAULT_HECIBAR   ((u8 *)0xfed17000)
 
#define MAINBOARD_POWER_OFF   0
 
#define MAINBOARD_POWER_ON   1
 
#define MAINBOARD_POWER_KEEP   2
 
#define UPRWC   0x3c
 
#define UPRWC_WR_EN   (1 << 1) /* USB Per-Port Registers Write Enable */
 
#define PSTS   0x06
 
#define SMLT   0x1b
 
#define SECSTS   0x1e
 
#define INTR   0x3c
 
#define PCH_EHCI1_DEV   PCI_DEV(0, 0x1d, 0)
 
#define PCH_EHCI2_DEV   PCI_DEV(0, 0x1a, 0)
 
#define PCH_XHCI_DEV   PCI_DEV(0, 0x14, 0)
 
#define PCH_ME_DEV   PCI_DEV(0, 0x16, 0)
 
#define PCH_PCIE_DEV_SLOT   28
 
#define PCH_LPC_DEV   PCI_DEV(0, 0x1f, 0)
 
#define SERIRQ_CNTL   0x64
 
#define GEN_PMCON_1   0xa0
 
#define GEN_PMCON_2   0xa2
 
#define GEN_PMCON_3   0xa4
 
#define ETR3   0xac
 
#define ETR3_CWORWRE   (1 << 18)
 
#define ETR3_CF9GR   (1 << 20)
 
#define CIR4   0xa9
 
#define PMIR   0xac
 
#define RTC_BATTERY_DEAD   (1 << 2)
 
#define RTC_POWER_FAILED   (1 << 1)
 
#define SLEEP_AFTER_POWER_FAIL   (1 << 0)
 
#define PMBASE   0x40
 
#define ACPI_CNTL   0x44
 
#define ACPI_EN   (1 << 7)
 
#define BIOS_CNTL   0xDC
 
#define GPIO_BASE   0x48 /* LPC GPIO Base Address Register */
 
#define GPIO_CNTL   0x4C /* LPC GPIO Control Register */
 
#define GPIO_ROUT   0xb8
 
#define GPI_DISABLE   0x00
 
#define GPI_IS_SMI   0x01
 
#define GPI_IS_SCI   0x02
 
#define GPI_IS_NMI   0x03
 
#define PIRQA_ROUT   0x60
 
#define PIRQB_ROUT   0x61
 
#define PIRQC_ROUT   0x62
 
#define PIRQD_ROUT   0x63
 
#define PIRQE_ROUT   0x68
 
#define PIRQF_ROUT   0x69
 
#define PIRQG_ROUT   0x6A
 
#define PIRQH_ROUT   0x6B
 
#define LPC_IO_DEC   0x80 /* IO Decode Ranges Register */
 
#define LPC_EN   0x82 /* LPC IF Enables Register */
 
#define CNF2_LPC_EN   (1 << 13) /* 0x4e/0x4f */
 
#define CNF1_LPC_EN   (1 << 12) /* 0x2e/0x2f */
 
#define MC_LPC_EN   (1 << 11) /* 0x62/0x66 */
 
#define KBC_LPC_EN   (1 << 10) /* 0x60/0x64 */
 
#define GAMEH_LPC_EN   (1 << 9) /* 0x208/0x20f */
 
#define GAMEL_LPC_EN   (1 << 8) /* 0x200/0x207 */
 
#define FDD_LPC_EN   (1 << 3) /* LPC_IO_DEC[12] */
 
#define LPT_LPC_EN   (1 << 2) /* LPC_IO_DEC[9:8] */
 
#define COMB_LPC_EN   (1 << 1) /* LPC_IO_DEC[6:4] */
 
#define COMA_LPC_EN   (1 << 0) /* LPC_IO_DEC[3:2] */
 
#define LPC_GEN1_DEC   0x84 /* LPC IF Generic Decode Range 1 */
 
#define LPC_GEN2_DEC   0x88 /* LPC IF Generic Decode Range 2 */
 
#define LPC_GEN3_DEC   0x8c /* LPC IF Generic Decode Range 3 */
 
#define LPC_GEN4_DEC   0x90 /* LPC IF Generic Decode Range 4 */
 
#define PCH_SATA_DEV   PCI_DEV(0, 0x1f, 2)
 
#define PCH_SATA2_DEV   PCI_DEV(0, 0x1f, 5)
 
#define INTR_LN   0x3c
 
#define IDE_TIM_PRI   0x40 /* IDE timings, primary */
 
#define IDE_DECODE_ENABLE   (1 << 15)
 
#define IDE_TIM_SEC   0x42 /* IDE timings, secondary */
 
#define SATA_SIRI   0xa0 /* SATA Indexed Register Index */
 
#define SATA_SIRD   0xa4 /* SATA Indexed Register Data */
 
#define SATA_SP   0xd0 /* Scratchpad */
 
#define SATA_IOBP_SP0G3IR   0xea000151
 
#define SATA_IOBP_SP1G3IR   0xea000051
 
#define PCH_SMBUS_DEV   PCI_DEV(0, 0x1f, 3)
 
#define SMB_BASE   0x20
 
#define HOSTC   0x40
 
#define I2C_EN   (1 << 2)
 
#define SMB_SMI_EN   (1 << 1)
 
#define HST_EN   (1 << 0)
 
#define GPIOBASE   0x48
 
#define PMBASE   0x40
 
#define VCH   0x0000 /* 32bit */
 
#define VCAP1   0x0004 /* 32bit */
 
#define VCAP2   0x0008 /* 32bit */
 
#define PVC   0x000c /* 16bit */
 
#define PVS   0x000e /* 16bit */
 
#define V0CAP   0x0010 /* 32bit */
 
#define V0CTL   0x0014 /* 32bit */
 
#define V0STS   0x001a /* 16bit */
 
#define V1CAP   0x001c /* 32bit */
 
#define V1CTL   0x0020 /* 32bit */
 
#define V1STS   0x0026 /* 16bit */
 
#define RCTCL   0x0100 /* 32bit */
 
#define ESD   0x0104 /* 32bit */
 
#define ULD   0x0110 /* 32bit */
 
#define ULBA   0x0118 /* 64bit */
 
#define RP1D   0x0120 /* 32bit */
 
#define RP1BA   0x0128 /* 64bit */
 
#define RP2D   0x0130 /* 32bit */
 
#define RP2BA   0x0138 /* 64bit */
 
#define RP3D   0x0140 /* 32bit */
 
#define RP3BA   0x0148 /* 64bit */
 
#define RP4D   0x0150 /* 32bit */
 
#define RP4BA   0x0158 /* 64bit */
 
#define HDD   0x0160 /* 32bit */
 
#define HDBA   0x0168 /* 64bit */
 
#define RP5D   0x0170 /* 32bit */
 
#define RP5BA   0x0178 /* 64bit */
 
#define RP6D   0x0180 /* 32bit */
 
#define RP6BA   0x0188 /* 64bit */
 
#define RPC   0x0400 /* 32bit */
 
#define RPFN   0x0404 /* 32bit */
 
#define RPFN_HIDE(port)   (1 << (((port) * 4) + 3))
 
#define RPFN_FNGET(reg, port)   (((reg) >> ((port) * 4)) & 7)
 
#define RPFN_FNSET(port, func)   (((func) & 7) << ((port) * 4))
 
#define RPFN_FNMASK(port)   (7 << ((port) * 4))
 
#define TRSR   0x1e00 /* 8bit */
 
#define TRCR   0x1e10 /* 64bit */
 
#define TWDR   0x1e18 /* 64bit */
 
#define IOTR0   0x1e80 /* 64bit */
 
#define IOTR1   0x1e88 /* 64bit */
 
#define IOTR2   0x1e90 /* 64bit */
 
#define IOTR3   0x1e98 /* 64bit */
 
#define TCTL   0x3000 /* 8bit */
 
#define NOINT   0
 
#define INTA   1
 
#define INTB   2
 
#define INTC   3
 
#define INTD   4
 
#define DIR_IDR   12 /* Interrupt D Pin Offset */
 
#define DIR_ICR   8 /* Interrupt C Pin Offset */
 
#define DIR_IBR   4 /* Interrupt B Pin Offset */
 
#define DIR_IAR   0 /* Interrupt A Pin Offset */
 
#define PIRQA   0
 
#define PIRQB   1
 
#define PIRQC   2
 
#define PIRQD   3
 
#define PIRQE   4
 
#define PIRQF   5
 
#define PIRQG   6
 
#define PIRQH   7
 
#define IOBPIRI   0x2330
 
#define IOBPD   0x2334
 
#define IOBPS   0x2338
 
#define IOBPS_RW_BX   ((1 << 9)|(1 << 10))
 
#define IOBPS_WRITE_AX   ((1 << 9)|(1 << 10))
 
#define IOBPS_READ_AX   ((1 << 8)|(1 << 9)|(1 << 10))
 
#define D31IP   0x3100 /* 32bit */
 
#define D31IP_TTIP   24 /* Thermal Throttle Pin */
 
#define D31IP_SIP2   20 /* SATA Pin 2 */
 
#define D31IP_UNKIP   16
 
#define D31IP_SMIP   12 /* SMBUS Pin */
 
#define D31IP_SIP   8 /* SATA Pin */
 
#define D30IP   0x3104 /* 32bit */
 
#define D30IP_PIP   0 /* PCI Bridge Pin */
 
#define D29IP   0x3108 /* 32bit */
 
#define D29IP_E1P   0 /* EHCI #1 Pin */
 
#define D28IP   0x310c /* 32bit */
 
#define D28IP_P8IP   28 /* PCI Express Port 8 */
 
#define D28IP_P7IP   24 /* PCI Express Port 7 */
 
#define D28IP_P6IP   20 /* PCI Express Port 6 */
 
#define D28IP_P5IP   16 /* PCI Express Port 5 */
 
#define D28IP_P4IP   12 /* PCI Express Port 4 */
 
#define D28IP_P3IP   8 /* PCI Express Port 3 */
 
#define D28IP_P2IP   4 /* PCI Express Port 2 */
 
#define D28IP_P1IP   0 /* PCI Express Port 1 */
 
#define D27IP   0x3110 /* 32bit */
 
#define D27IP_ZIP   0 /* HD Audio Pin */
 
#define D26IP   0x3114 /* 32bit */
 
#define D26IP_E2P   0 /* EHCI #2 Pin */
 
#define D25IP   0x3118 /* 32bit */
 
#define D25IP_LIP   0 /* GbE LAN Pin */
 
#define D22IP   0x3124 /* 32bit */
 
#define D22IP_KTIP   12 /* KT Pin */
 
#define D22IP_IDERIP   8 /* IDE-R Pin */
 
#define D22IP_MEI2IP   4 /* MEI #2 Pin */
 
#define D22IP_MEI1IP   0 /* MEI #1 Pin */
 
#define D20IP   0x3128 /* 32bit */
 
#define D20IP_XHCIIP   0
 
#define D31IR   0x3140 /* 16bit */
 
#define D30IR   0x3142 /* 16bit */
 
#define D29IR   0x3144 /* 16bit */
 
#define D28IR   0x3146 /* 16bit */
 
#define D27IR   0x3148 /* 16bit */
 
#define D26IR   0x314c /* 16bit */
 
#define D25IR   0x3150 /* 16bit */
 
#define D22IR   0x315c /* 16bit */
 
#define D20IR   0x3160 /* 16bit */
 
#define OIC   0x31fe /* 16bit */
 
#define SOFT_RESET_CTRL   0x38f4
 
#define SOFT_RESET_DATA   0x38f8
 
#define PRSTS   0x3310
 
#define CIR6   0x2024
 
#define CIR7   0x3314
 
#define CIR8   0x3324
 
#define CIR9   0x3330
 
#define CIR10   0x3340
 
#define CIR13   0x3350
 
#define CIR14   0x3368
 
#define CIR15   0x3378
 
#define CIR16   0x3388
 
#define CIR17   0x33a0
 
#define CIR18   0x33a8
 
#define CIR19   0x33c0
 
#define CIR20   0x33cc
 
#define CIR21   0x33d0
 
#define CIR22   0x33d4
 
#define DIR_ROUTE(x, a, b, c, d)
 
#define RC   0x3400 /* 32bit */
 
#define HPTC   0x3404 /* 32bit */
 
#define GCS   0x3410 /* 32bit */
 
#define BUC   0x3414 /* 32bit */
 
#define PCH_DISABLE_GBE   (1 << 5)
 
#define FD   0x3418 /* 32bit */
 
#define DISPBDF   0x3424 /* 16bit */
 
#define FD2   0x3428 /* 32bit */
 
#define CG   0x341c /* 32bit */
 
#define PCH_DISABLE_ALWAYS   ((1 << 0)|(1 << 26))
 
#define PCH_DISABLE_P2P   (1 << 1)
 
#define PCH_DISABLE_SATA1   (1 << 2)
 
#define PCH_DISABLE_SMBUS   (1 << 3)
 
#define PCH_DISABLE_HD_AUDIO   (1 << 4)
 
#define PCH_DISABLE_EHCI2   (1 << 13)
 
#define PCH_DISABLE_LPC   (1 << 14)
 
#define PCH_DISABLE_EHCI1   (1 << 15)
 
#define PCH_DISABLE_PCIE(x)   (1 << (16 + x))
 
#define PCH_DISABLE_THERMAL   (1 << 24)
 
#define PCH_DISABLE_SATA2   (1 << 25)
 
#define PCH_DISABLE_XHCI   (1 << 27)
 
#define PCH_DISABLE_KT   (1 << 4)
 
#define PCH_DISABLE_IDER   (1 << 3)
 
#define PCH_DISABLE_MEI2   (1 << 2)
 
#define PCH_DISABLE_MEI1   (1 << 1)
 
#define PCH_ENABLE_DBDF   (1 << 0)
 
#define USBIR0   0x3500 /* 32bit */
 
#define USBIR1   0x3504 /* 32bit */
 
#define USBIR2   0x3508 /* 32bit */
 
#define USBIR3   0x350c /* 32bit */
 
#define USBIR4   0x3510 /* 32bit */
 
#define USBIR5   0x3514 /* 32bit */
 
#define USBIR6   0x3518 /* 32bit */
 
#define USBIR7   0x351c /* 32bit */
 
#define USBIR8   0x3520 /* 32bit */
 
#define USBIR9   0x3524 /* 32bit */
 
#define USBIR10   0x3528 /* 32bit */
 
#define USBIR11   0x352c /* 32bit */
 
#define USBIR12   0x3530 /* 32bit */
 
#define USBIR13   0x3534 /* 32bit */
 
#define USBIRC   0x3564 /* 32bit */
 
#define USBIRA   0x3570 /* 32bit */
 
#define USBIRB   0x357c /* 32bit */
 
#define MISCCTL   0x3590 /* 32bit */
 
#define USBPDO   0x359c /* 32bit */
 
#define USBOCM1   0x35a0 /* 32bit */
 
#define USBOCM2   0x35a4 /* 32bit */
 
#define RMHWKCTL   0x35b0 /* 32bit */
 
#define PM1_STS   0x00
 
#define WAK_STS   (1 << 15)
 
#define PCIEXPWAK_STS   (1 << 14)
 
#define PRBTNOR_STS   (1 << 11)
 
#define RTC_STS   (1 << 10)
 
#define PWRBTN_STS   (1 << 8)
 
#define GBL_STS   (1 << 5)
 
#define BM_STS   (1 << 4)
 
#define TMROF_STS   (1 << 0)
 
#define PM1_EN   0x02
 
#define PCIEXPWAK_DIS   (1 << 14)
 
#define RTC_EN   (1 << 10)
 
#define PWRBTN_EN   (1 << 8)
 
#define GBL_EN   (1 << 5)
 
#define TMROF_EN   (1 << 0)
 
#define PM1_CNT   0x04
 
#define GBL_RLS   (1 << 2)
 
#define BM_RLD   (1 << 1)
 
#define SCI_EN   (1 << 0)
 
#define PM1_TMR   0x08
 
#define PROC_CNT   0x10
 
#define LV2   0x14
 
#define LV3   0x15
 
#define LV4   0x16
 
#define PM2_CNT   0x50
 
#define GPE0_STS   0x20
 
#define PME_B0_STS   (1 << 13)
 
#define PME_STS   (1 << 11)
 
#define BATLOW_STS   (1 << 10)
 
#define PCI_EXP_STS   (1 << 9)
 
#define RI_STS   (1 << 8)
 
#define SMB_WAK_STS   (1 << 7)
 
#define TCOSCI_STS   (1 << 6)
 
#define SWGPE_STS   (1 << 2)
 
#define HOT_PLUG_STS   (1 << 1)
 
#define GPE0_EN   0x28
 
#define PME_B0_EN   (1 << 13)
 
#define PME_EN   (1 << 11)
 
#define TCOSCI_EN   (1 << 6)
 
#define SMI_EN   0x30
 
#define INTEL_USB2_EN   (1 << 18)
 
#define LEGACY_USB2_EN   (1 << 17)
 
#define PERIODIC_EN   (1 << 14)
 
#define TCO_EN   (1 << 13)
 
#define MCSMI_EN   (1 << 11)
 
#define BIOS_RLS   (1 << 7)
 
#define SWSMI_TMR_EN   (1 << 6)
 
#define APMC_EN   (1 << 5)
 
#define SLP_SMI_EN   (1 << 4)
 
#define LEGACY_USB_EN   (1 << 3)
 
#define BIOS_EN   (1 << 2)
 
#define EOS   (1 << 1)
 
#define GBL_SMI_EN   (1 << 0)
 
#define SMI_STS   0x34
 
#define ALT_GP_SMI_EN   0x38
 
#define ALT_GP_SMI_STS   0x3a
 
#define GPE_CNTL   0x42
 
#define DEVACT_STS   0x44
 
#define SS_CNT   0x50
 
#define C3_RES   0x54
 
#define TCO1_STS   0x64
 
#define DMISCI_STS   (1 << 9)
 
#define TCO2_STS   0x66
 
#define SPIBAR_HSFS   0x3804 /* SPI hardware sequence status */
 
#define SPIBAR_HSFS_SCIP   (1 << 5) /* SPI Cycle In Progress */
 
#define SPIBAR_HSFS_AEL   (1 << 2) /* SPI Access Error Log */
 
#define SPIBAR_HSFS_FCERR   (1 << 1) /* SPI Flash Cycle Error */
 
#define SPIBAR_HSFS_FDONE   (1 << 0) /* SPI Flash Cycle Done */
 
#define SPIBAR_HSFC   0x3806 /* SPI hardware sequence control */
 
#define SPIBAR_HSFC_BYTE_COUNT(c)   (((c - 1) & 0x3f) << 8)
 
#define SPIBAR_HSFC_CYCLE_READ   (0 << 1) /* Read cycle */
 
#define SPIBAR_HSFC_CYCLE_WRITE   (2 << 1) /* Write cycle */
 
#define SPIBAR_HSFC_CYCLE_ERASE   (3 << 1) /* Erase cycle */
 
#define SPIBAR_HSFC_GO   (1 << 0) /* GO: start SPI transaction */
 
#define SPIBAR_FADDR   0x3808 /* SPI flash address */
 
#define SPIBAR_FDATA(n)   (0x3810 + (4 * n)) /* SPI flash data */
 

Enumerations

enum  current_lookup_idx {
  IF1_F57 = 0 , IF1_F5F , IF1_753 , IF1_75F ,
  IF1_14B , IF1_74B , IF1_557 , IF1_757 ,
  IF1_55F , IF1_54B
}
 

Functions

void pch_iobp_update (u32 address, u32 andvalue, u32 orvalue)
 
void enable_usb_bar (void)
 
void ibexpeak_setup_bars (void)
 
void early_pch_init (void)
 
void early_thermal_init (void)
 
void southbridge_configure_default_intmap (void)
 
void pch_setup_cir (int chipset_type)
 
void early_usb_init (const struct southbridge_usb_port *portmap)
 
void pch_enable (struct device *dev)
 

Variables

const struct southbridge_usb_port mainboard_usb_ports [14]
 

Macro Definition Documentation

◆ ACPI_CNTL

#define ACPI_CNTL   0x44

Definition at line 106 of file pch.h.

◆ ACPI_EN

#define ACPI_EN   (1 << 7)

Definition at line 107 of file pch.h.

◆ ALT_GP_SMI_EN

#define ALT_GP_SMI_EN   0x38

Definition at line 443 of file pch.h.

◆ ALT_GP_SMI_STS

#define ALT_GP_SMI_STS   0x3a

Definition at line 444 of file pch.h.

◆ APMC_EN

#define APMC_EN   (1 << 5)

Definition at line 436 of file pch.h.

◆ BATLOW_STS

#define BATLOW_STS   (1 << 10)

Definition at line 417 of file pch.h.

◆ BIOS_CNTL

#define BIOS_CNTL   0xDC

Definition at line 108 of file pch.h.

◆ BIOS_EN

#define BIOS_EN   (1 << 2)

Definition at line 439 of file pch.h.

◆ BIOS_RLS

#define BIOS_RLS   (1 << 7)

Definition at line 434 of file pch.h.

◆ BM_RLD

#define BM_RLD   (1 << 1)

Definition at line 406 of file pch.h.

◆ BM_STS

#define BM_STS   (1 << 4)

Definition at line 396 of file pch.h.

◆ BUC

#define BUC   0x3414 /* 32bit */

Definition at line 330 of file pch.h.

◆ C3_RES

#define C3_RES   0x54

Definition at line 448 of file pch.h.

◆ CG

#define CG   0x341c /* 32bit */

Definition at line 335 of file pch.h.

◆ CIR10

#define CIR10   0x3340

Definition at line 311 of file pch.h.

◆ CIR13

#define CIR13   0x3350

Definition at line 312 of file pch.h.

◆ CIR14

#define CIR14   0x3368

Definition at line 313 of file pch.h.

◆ CIR15

#define CIR15   0x3378

Definition at line 314 of file pch.h.

◆ CIR16

#define CIR16   0x3388

Definition at line 315 of file pch.h.

◆ CIR17

#define CIR17   0x33a0

Definition at line 316 of file pch.h.

◆ CIR18

#define CIR18   0x33a8

Definition at line 317 of file pch.h.

◆ CIR19

#define CIR19   0x33c0

Definition at line 318 of file pch.h.

◆ CIR20

#define CIR20   0x33cc

Definition at line 319 of file pch.h.

◆ CIR21

#define CIR21   0x33d0

Definition at line 320 of file pch.h.

◆ CIR22

#define CIR22   0x33d4

Definition at line 321 of file pch.h.

◆ CIR4

#define CIR4   0xa9

Definition at line 97 of file pch.h.

◆ CIR6

#define CIR6   0x2024

Definition at line 307 of file pch.h.

◆ CIR7

#define CIR7   0x3314

Definition at line 308 of file pch.h.

◆ CIR8

#define CIR8   0x3324

Definition at line 309 of file pch.h.

◆ CIR9

#define CIR9   0x3330

Definition at line 310 of file pch.h.

◆ CNF1_LPC_EN

#define CNF1_LPC_EN   (1 << 12) /* 0x2e/0x2f */

Definition at line 130 of file pch.h.

◆ CNF2_LPC_EN

#define CNF2_LPC_EN   (1 << 13) /* 0x4e/0x4f */

Definition at line 129 of file pch.h.

◆ COMA_LPC_EN

#define COMA_LPC_EN   (1 << 0) /* LPC_IO_DEC[3:2] */

Definition at line 138 of file pch.h.

◆ COMB_LPC_EN

#define COMB_LPC_EN   (1 << 1) /* LPC_IO_DEC[6:4] */

Definition at line 137 of file pch.h.

◆ D20IP

#define D20IP   0x3128 /* 32bit */

Definition at line 291 of file pch.h.

◆ D20IP_XHCIIP

#define D20IP_XHCIIP   0

Definition at line 292 of file pch.h.

◆ D20IR

#define D20IR   0x3160 /* 16bit */

Definition at line 301 of file pch.h.

◆ D22IP

#define D22IP   0x3124 /* 32bit */

Definition at line 286 of file pch.h.

◆ D22IP_IDERIP

#define D22IP_IDERIP   8 /* IDE-R Pin */

Definition at line 288 of file pch.h.

◆ D22IP_KTIP

#define D22IP_KTIP   12 /* KT Pin */

Definition at line 287 of file pch.h.

◆ D22IP_MEI1IP

#define D22IP_MEI1IP   0 /* MEI #1 Pin */

Definition at line 290 of file pch.h.

◆ D22IP_MEI2IP

#define D22IP_MEI2IP   4 /* MEI #2 Pin */

Definition at line 289 of file pch.h.

◆ D22IR

#define D22IR   0x315c /* 16bit */

Definition at line 300 of file pch.h.

◆ D25IP

#define D25IP   0x3118 /* 32bit */

Definition at line 284 of file pch.h.

◆ D25IP_LIP

#define D25IP_LIP   0 /* GbE LAN Pin */

Definition at line 285 of file pch.h.

◆ D25IR

#define D25IR   0x3150 /* 16bit */

Definition at line 299 of file pch.h.

◆ D26IP

#define D26IP   0x3114 /* 32bit */

Definition at line 282 of file pch.h.

◆ D26IP_E2P

#define D26IP_E2P   0 /* EHCI #2 Pin */

Definition at line 283 of file pch.h.

◆ D26IR

#define D26IR   0x314c /* 16bit */

Definition at line 298 of file pch.h.

◆ D27IP

#define D27IP   0x3110 /* 32bit */

Definition at line 280 of file pch.h.

◆ D27IP_ZIP

#define D27IP_ZIP   0 /* HD Audio Pin */

Definition at line 281 of file pch.h.

◆ D27IR

#define D27IR   0x3148 /* 16bit */

Definition at line 297 of file pch.h.

◆ D28IP

#define D28IP   0x310c /* 32bit */

Definition at line 271 of file pch.h.

◆ D28IP_P1IP

#define D28IP_P1IP   0 /* PCI Express Port 1 */

Definition at line 279 of file pch.h.

◆ D28IP_P2IP

#define D28IP_P2IP   4 /* PCI Express Port 2 */

Definition at line 278 of file pch.h.

◆ D28IP_P3IP

#define D28IP_P3IP   8 /* PCI Express Port 3 */

Definition at line 277 of file pch.h.

◆ D28IP_P4IP

#define D28IP_P4IP   12 /* PCI Express Port 4 */

Definition at line 276 of file pch.h.

◆ D28IP_P5IP

#define D28IP_P5IP   16 /* PCI Express Port 5 */

Definition at line 275 of file pch.h.

◆ D28IP_P6IP

#define D28IP_P6IP   20 /* PCI Express Port 6 */

Definition at line 274 of file pch.h.

◆ D28IP_P7IP

#define D28IP_P7IP   24 /* PCI Express Port 7 */

Definition at line 273 of file pch.h.

◆ D28IP_P8IP

#define D28IP_P8IP   28 /* PCI Express Port 8 */

Definition at line 272 of file pch.h.

◆ D28IR

#define D28IR   0x3146 /* 16bit */

Definition at line 296 of file pch.h.

◆ D29IP

#define D29IP   0x3108 /* 32bit */

Definition at line 269 of file pch.h.

◆ D29IP_E1P

#define D29IP_E1P   0 /* EHCI #1 Pin */

Definition at line 270 of file pch.h.

◆ D29IR

#define D29IR   0x3144 /* 16bit */

Definition at line 295 of file pch.h.

◆ D30IP

#define D30IP   0x3104 /* 32bit */

Definition at line 267 of file pch.h.

◆ D30IP_PIP

#define D30IP_PIP   0 /* PCI Bridge Pin */

Definition at line 268 of file pch.h.

◆ D30IR

#define D30IR   0x3142 /* 16bit */

Definition at line 294 of file pch.h.

◆ D31IP

#define D31IP   0x3100 /* 32bit */

Definition at line 261 of file pch.h.

◆ D31IP_SIP

#define D31IP_SIP   8 /* SATA Pin */

Definition at line 266 of file pch.h.

◆ D31IP_SIP2

#define D31IP_SIP2   20 /* SATA Pin 2 */

Definition at line 263 of file pch.h.

◆ D31IP_SMIP

#define D31IP_SMIP   12 /* SMBUS Pin */

Definition at line 265 of file pch.h.

◆ D31IP_TTIP

#define D31IP_TTIP   24 /* Thermal Throttle Pin */

Definition at line 262 of file pch.h.

◆ D31IP_UNKIP

#define D31IP_UNKIP   16

Definition at line 264 of file pch.h.

◆ D31IR

#define D31IR   0x3140 /* 16bit */

Definition at line 293 of file pch.h.

◆ DEFAULT_GPIOBASE

#define DEFAULT_GPIOBASE   0x0480

Definition at line 23 of file pch.h.

◆ DEFAULT_HECIBAR

#define DEFAULT_HECIBAR   ((u8 *)0xfed17000)

Definition at line 25 of file pch.h.

◆ DEFAULT_PMBASE

#define DEFAULT_PMBASE   0x0500

Definition at line 24 of file pch.h.

◆ DEVACT_STS

#define DEVACT_STS   0x44

Definition at line 446 of file pch.h.

◆ DIR_IAR

#define DIR_IAR   0 /* Interrupt A Pin Offset */

Definition at line 242 of file pch.h.

◆ DIR_IBR

#define DIR_IBR   4 /* Interrupt B Pin Offset */

Definition at line 241 of file pch.h.

◆ DIR_ICR

#define DIR_ICR   8 /* Interrupt C Pin Offset */

Definition at line 240 of file pch.h.

◆ DIR_IDR

#define DIR_IDR   12 /* Interrupt D Pin Offset */

Definition at line 239 of file pch.h.

◆ DIR_ROUTE

#define DIR_ROUTE (   x,
  a,
  b,
  c,
  d 
)
Value:
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
((b) << DIR_IBR) | ((a) << DIR_IAR))
x
int x
Definition: edid.c:994
RCBA32
#define RCBA32(x)
Definition: rcba.h:14
DIR_ICR
#define DIR_ICR
Definition: pch.h:240
DIR_IDR
#define DIR_IDR
Definition: pch.h:239
DIR_IAR
#define DIR_IAR
Definition: pch.h:242
DIR_IBR
#define DIR_IBR
Definition: pch.h:241
c
#define c(value, pmcreg, dst_bits)

Definition at line 323 of file pch.h.

◆ DISPBDF

#define DISPBDF   0x3424 /* 16bit */

Definition at line 333 of file pch.h.

◆ DMISCI_STS

#define DMISCI_STS   (1 << 9)

Definition at line 450 of file pch.h.

◆ EOS

#define EOS   (1 << 1)

Definition at line 440 of file pch.h.

◆ ESD

#define ESD   0x0104 /* 32bit */

Definition at line 191 of file pch.h.

◆ ETR3

#define ETR3   0xac

Definition at line 93 of file pch.h.

◆ ETR3_CF9GR

#define ETR3_CF9GR   (1 << 20)

Definition at line 95 of file pch.h.

◆ ETR3_CWORWRE

#define ETR3_CWORWRE   (1 << 18)

Definition at line 94 of file pch.h.

◆ FD

#define FD   0x3418 /* 32bit */

Definition at line 332 of file pch.h.

◆ FD2

#define FD2   0x3428 /* 32bit */

Definition at line 334 of file pch.h.

◆ FDD_LPC_EN

#define FDD_LPC_EN   (1 << 3) /* LPC_IO_DEC[12] */

Definition at line 135 of file pch.h.

◆ GAMEH_LPC_EN

#define GAMEH_LPC_EN   (1 << 9) /* 0x208/0x20f */

Definition at line 133 of file pch.h.

◆ GAMEL_LPC_EN

#define GAMEL_LPC_EN   (1 << 8) /* 0x200/0x207 */

Definition at line 134 of file pch.h.

◆ GBL_EN

#define GBL_EN   (1 << 5)

Definition at line 402 of file pch.h.

◆ GBL_RLS

#define GBL_RLS   (1 << 2)

Definition at line 405 of file pch.h.

◆ GBL_SMI_EN

#define GBL_SMI_EN   (1 << 0)

Definition at line 441 of file pch.h.

◆ GBL_STS

#define GBL_STS   (1 << 5)

Definition at line 395 of file pch.h.

◆ GCS

#define GCS   0x3410 /* 32bit */

Definition at line 329 of file pch.h.

◆ GEN_PMCON_1

#define GEN_PMCON_1   0xa0

Definition at line 90 of file pch.h.

◆ GEN_PMCON_2

#define GEN_PMCON_2   0xa2

Definition at line 91 of file pch.h.

◆ GEN_PMCON_3

#define GEN_PMCON_3   0xa4

Definition at line 92 of file pch.h.

◆ GPE0_EN

#define GPE0_EN   0x28

Definition at line 424 of file pch.h.

◆ GPE0_STS

#define GPE0_STS   0x20

Definition at line 414 of file pch.h.

◆ GPE_CNTL

#define GPE_CNTL   0x42

Definition at line 445 of file pch.h.

◆ GPI_DISABLE

#define GPI_DISABLE   0x00

Definition at line 113 of file pch.h.

◆ GPI_IS_NMI

#define GPI_IS_NMI   0x03

Definition at line 116 of file pch.h.

◆ GPI_IS_SCI

#define GPI_IS_SCI   0x02

Definition at line 115 of file pch.h.

◆ GPI_IS_SMI

#define GPI_IS_SMI   0x01

Definition at line 114 of file pch.h.

◆ GPIO_BASE

#define GPIO_BASE   0x48 /* LPC GPIO Base Address Register */

Definition at line 109 of file pch.h.

◆ GPIO_CNTL

#define GPIO_CNTL   0x4C /* LPC GPIO Control Register */

Definition at line 110 of file pch.h.

◆ GPIO_ROUT

#define GPIO_ROUT   0xb8

Definition at line 112 of file pch.h.

◆ GPIOBASE

#define GPIOBASE   0x48

Definition at line 172 of file pch.h.

◆ HDBA

#define HDBA   0x0168 /* 64bit */

Definition at line 204 of file pch.h.

◆ HDD

#define HDD   0x0160 /* 32bit */

Definition at line 203 of file pch.h.

◆ HOSTC

#define HOSTC   0x40

Definition at line 163 of file pch.h.

◆ HOT_PLUG_STS

#define HOT_PLUG_STS   (1 << 1)

Definition at line 423 of file pch.h.

◆ HPTC

#define HPTC   0x3404 /* 32bit */

Definition at line 328 of file pch.h.

◆ HST_EN

#define HST_EN   (1 << 0)

Definition at line 168 of file pch.h.

◆ I2C_EN

#define I2C_EN   (1 << 2)

Definition at line 166 of file pch.h.

◆ IDE_DECODE_ENABLE

#define IDE_DECODE_ENABLE   (1 << 15)

Definition at line 149 of file pch.h.

◆ IDE_TIM_PRI

#define IDE_TIM_PRI   0x40 /* IDE timings, primary */

Definition at line 148 of file pch.h.

◆ IDE_TIM_SEC

#define IDE_TIM_SEC   0x42 /* IDE timings, secondary */

Definition at line 150 of file pch.h.

◆ INTA

#define INTA   1

Definition at line 234 of file pch.h.

◆ INTB

#define INTB   2

Definition at line 235 of file pch.h.

◆ INTC

#define INTC   3

Definition at line 236 of file pch.h.

◆ INTD

#define INTD   4

Definition at line 237 of file pch.h.

◆ INTEL_USB2_EN

#define INTEL_USB2_EN   (1 << 18)

Definition at line 429 of file pch.h.

◆ INTR

#define INTR   0x3c

Definition at line 78 of file pch.h.

◆ INTR_LN

#define INTR_LN   0x3c

Definition at line 147 of file pch.h.

◆ IOBPD

#define IOBPD   0x2334

Definition at line 255 of file pch.h.

◆ IOBPIRI

#define IOBPIRI   0x2330

Definition at line 254 of file pch.h.

◆ IOBPS

#define IOBPS   0x2338

Definition at line 256 of file pch.h.

◆ IOBPS_READ_AX

#define IOBPS_READ_AX   ((1 << 8)|(1 << 9)|(1 << 10))

Definition at line 259 of file pch.h.

◆ IOBPS_RW_BX

#define IOBPS_RW_BX   ((1 << 9)|(1 << 10))

Definition at line 257 of file pch.h.

◆ IOBPS_WRITE_AX

#define IOBPS_WRITE_AX   ((1 << 9)|(1 << 10))

Definition at line 258 of file pch.h.

◆ IOTR0

#define IOTR0   0x1e80 /* 64bit */

Definition at line 226 of file pch.h.

◆ IOTR1

#define IOTR1   0x1e88 /* 64bit */

Definition at line 227 of file pch.h.

◆ IOTR2

#define IOTR2   0x1e90 /* 64bit */

Definition at line 228 of file pch.h.

◆ IOTR3

#define IOTR3   0x1e98 /* 64bit */

Definition at line 229 of file pch.h.

◆ KBC_LPC_EN

#define KBC_LPC_EN   (1 << 10) /* 0x60/0x64 */

Definition at line 132 of file pch.h.

◆ LEGACY_USB2_EN

#define LEGACY_USB2_EN   (1 << 17)

Definition at line 430 of file pch.h.

◆ LEGACY_USB_EN

#define LEGACY_USB_EN   (1 << 3)

Definition at line 438 of file pch.h.

◆ LPC_EN

#define LPC_EN   0x82 /* LPC IF Enables Register */

Definition at line 128 of file pch.h.

◆ LPC_GEN1_DEC

#define LPC_GEN1_DEC   0x84 /* LPC IF Generic Decode Range 1 */

Definition at line 139 of file pch.h.

◆ LPC_GEN2_DEC

#define LPC_GEN2_DEC   0x88 /* LPC IF Generic Decode Range 2 */

Definition at line 140 of file pch.h.

◆ LPC_GEN3_DEC

#define LPC_GEN3_DEC   0x8c /* LPC IF Generic Decode Range 3 */

Definition at line 141 of file pch.h.

◆ LPC_GEN4_DEC

#define LPC_GEN4_DEC   0x90 /* LPC IF Generic Decode Range 4 */

Definition at line 142 of file pch.h.

◆ LPC_IO_DEC

#define LPC_IO_DEC   0x80 /* IO Decode Ranges Register */

Definition at line 127 of file pch.h.

◆ LPT_LPC_EN

#define LPT_LPC_EN   (1 << 2) /* LPC_IO_DEC[9:8] */

Definition at line 136 of file pch.h.

◆ LV2

#define LV2   0x14

Definition at line 410 of file pch.h.

◆ LV3

#define LV3   0x15

Definition at line 411 of file pch.h.

◆ LV4

#define LV4   0x16

Definition at line 412 of file pch.h.

◆ MAINBOARD_POWER_KEEP

#define MAINBOARD_POWER_KEEP   2

Definition at line 68 of file pch.h.

◆ MAINBOARD_POWER_OFF

#define MAINBOARD_POWER_OFF   0

Definition at line 66 of file pch.h.

◆ MAINBOARD_POWER_ON

#define MAINBOARD_POWER_ON   1

Definition at line 67 of file pch.h.

◆ MC_LPC_EN

#define MC_LPC_EN   (1 << 11) /* 0x62/0x66 */

Definition at line 131 of file pch.h.

◆ MCSMI_EN

#define MCSMI_EN   (1 << 11)

Definition at line 433 of file pch.h.

◆ MISCCTL

#define MISCCTL   0x3590 /* 32bit */

Definition at line 379 of file pch.h.

◆ NOINT

#define NOINT   0

Definition at line 233 of file pch.h.

◆ OIC

#define OIC   0x31fe /* 16bit */

Definition at line 302 of file pch.h.

◆ PCH_DISABLE_ALWAYS

#define PCH_DISABLE_ALWAYS   ((1 << 0)|(1 << 26))

Definition at line 338 of file pch.h.

◆ PCH_DISABLE_EHCI1

#define PCH_DISABLE_EHCI1   (1 << 15)

Definition at line 345 of file pch.h.

◆ PCH_DISABLE_EHCI2

#define PCH_DISABLE_EHCI2   (1 << 13)

Definition at line 343 of file pch.h.

◆ PCH_DISABLE_GBE

#define PCH_DISABLE_GBE   (1 << 5)

Definition at line 331 of file pch.h.

◆ PCH_DISABLE_HD_AUDIO

#define PCH_DISABLE_HD_AUDIO   (1 << 4)

Definition at line 342 of file pch.h.

◆ PCH_DISABLE_IDER

#define PCH_DISABLE_IDER   (1 << 3)

Definition at line 353 of file pch.h.

◆ PCH_DISABLE_KT

#define PCH_DISABLE_KT   (1 << 4)

Definition at line 352 of file pch.h.

◆ PCH_DISABLE_LPC

#define PCH_DISABLE_LPC   (1 << 14)

Definition at line 344 of file pch.h.

◆ PCH_DISABLE_MEI1

#define PCH_DISABLE_MEI1   (1 << 1)

Definition at line 355 of file pch.h.

◆ PCH_DISABLE_MEI2

#define PCH_DISABLE_MEI2   (1 << 2)

Definition at line 354 of file pch.h.

◆ PCH_DISABLE_P2P

#define PCH_DISABLE_P2P   (1 << 1)

Definition at line 339 of file pch.h.

◆ PCH_DISABLE_PCIE

#define PCH_DISABLE_PCIE (   x)    (1 << (16 + x))

Definition at line 346 of file pch.h.

◆ PCH_DISABLE_SATA1

#define PCH_DISABLE_SATA1   (1 << 2)

Definition at line 340 of file pch.h.

◆ PCH_DISABLE_SATA2

#define PCH_DISABLE_SATA2   (1 << 25)

Definition at line 348 of file pch.h.

◆ PCH_DISABLE_SMBUS

#define PCH_DISABLE_SMBUS   (1 << 3)

Definition at line 341 of file pch.h.

◆ PCH_DISABLE_THERMAL

#define PCH_DISABLE_THERMAL   (1 << 24)

Definition at line 347 of file pch.h.

◆ PCH_DISABLE_XHCI

#define PCH_DISABLE_XHCI   (1 << 27)

Definition at line 349 of file pch.h.

◆ PCH_EHCI1_DEV

#define PCH_EHCI1_DEV   PCI_DEV(0, 0x1d, 0)

Definition at line 80 of file pch.h.

◆ PCH_EHCI2_DEV

#define PCH_EHCI2_DEV   PCI_DEV(0, 0x1a, 0)

Definition at line 81 of file pch.h.

◆ PCH_ENABLE_DBDF

#define PCH_ENABLE_DBDF   (1 << 0)

Definition at line 356 of file pch.h.

◆ PCH_LPC_DEV

#define PCH_LPC_DEV   PCI_DEV(0, 0x1f, 0)

Definition at line 87 of file pch.h.

◆ PCH_ME_DEV

#define PCH_ME_DEV   PCI_DEV(0, 0x16, 0)

Definition at line 83 of file pch.h.

◆ PCH_PCIE_DEV_SLOT

#define PCH_PCIE_DEV_SLOT   28

Definition at line 84 of file pch.h.

◆ PCH_SATA2_DEV

#define PCH_SATA2_DEV   PCI_DEV(0, 0x1f, 5)

Definition at line 146 of file pch.h.

◆ PCH_SATA_DEV

#define PCH_SATA_DEV   PCI_DEV(0, 0x1f, 2)

Definition at line 145 of file pch.h.

◆ PCH_SMBUS_DEV

#define PCH_SMBUS_DEV   PCI_DEV(0, 0x1f, 3)

Definition at line 161 of file pch.h.

◆ PCH_STEP_A0

#define PCH_STEP_A0   0

Definition at line 14 of file pch.h.

◆ PCH_STEP_A1

#define PCH_STEP_A1   1

Definition at line 15 of file pch.h.

◆ PCH_STEP_B0

#define PCH_STEP_B0   2

Definition at line 16 of file pch.h.

◆ PCH_STEP_B1

#define PCH_STEP_B1   3

Definition at line 17 of file pch.h.

◆ PCH_STEP_B2

#define PCH_STEP_B2   4

Definition at line 18 of file pch.h.

◆ PCH_STEP_B3

#define PCH_STEP_B3   5

Definition at line 19 of file pch.h.

◆ PCH_TYPE_CPT

#define PCH_TYPE_CPT   0x1c /* CougarPoint */

Definition at line 9 of file pch.h.

◆ PCH_TYPE_MOBILE5

#define PCH_TYPE_MOBILE5   0x3b

Definition at line 11 of file pch.h.

◆ PCH_TYPE_PPT

#define PCH_TYPE_PPT   0x1e /* IvyBridge */

Definition at line 10 of file pch.h.

◆ PCH_XHCI_DEV

#define PCH_XHCI_DEV   PCI_DEV(0, 0x14, 0)

Definition at line 82 of file pch.h.

◆ PCI_EXP_STS

#define PCI_EXP_STS   (1 << 9)

Definition at line 418 of file pch.h.

◆ PCIEXPWAK_DIS

#define PCIEXPWAK_DIS   (1 << 14)

Definition at line 399 of file pch.h.

◆ PCIEXPWAK_STS

#define PCIEXPWAK_STS   (1 << 14)

Definition at line 391 of file pch.h.

◆ PERIODIC_EN

#define PERIODIC_EN   (1 << 14)

Definition at line 431 of file pch.h.

◆ PIRQA

#define PIRQA   0

Definition at line 244 of file pch.h.

◆ PIRQA_ROUT

#define PIRQA_ROUT   0x60

Definition at line 118 of file pch.h.

◆ PIRQB

#define PIRQB   1

Definition at line 245 of file pch.h.

◆ PIRQB_ROUT

#define PIRQB_ROUT   0x61

Definition at line 119 of file pch.h.

◆ PIRQC

#define PIRQC   2

Definition at line 246 of file pch.h.

◆ PIRQC_ROUT

#define PIRQC_ROUT   0x62

Definition at line 120 of file pch.h.

◆ PIRQD

#define PIRQD   3

Definition at line 247 of file pch.h.

◆ PIRQD_ROUT

#define PIRQD_ROUT   0x63

Definition at line 121 of file pch.h.

◆ PIRQE

#define PIRQE   4

Definition at line 248 of file pch.h.

◆ PIRQE_ROUT

#define PIRQE_ROUT   0x68

Definition at line 122 of file pch.h.

◆ PIRQF

#define PIRQF   5

Definition at line 249 of file pch.h.

◆ PIRQF_ROUT

#define PIRQF_ROUT   0x69

Definition at line 123 of file pch.h.

◆ PIRQG

#define PIRQG   6

Definition at line 250 of file pch.h.

◆ PIRQG_ROUT

#define PIRQG_ROUT   0x6A

Definition at line 124 of file pch.h.

◆ PIRQH

#define PIRQH   7

Definition at line 251 of file pch.h.

◆ PIRQH_ROUT

#define PIRQH_ROUT   0x6B

Definition at line 125 of file pch.h.

◆ PM1_CNT

#define PM1_CNT   0x04

Definition at line 404 of file pch.h.

◆ PM1_EN

#define PM1_EN   0x02

Definition at line 398 of file pch.h.

◆ PM1_STS

#define PM1_STS   0x00

Definition at line 389 of file pch.h.

◆ PM1_TMR

#define PM1_TMR   0x08

Definition at line 408 of file pch.h.

◆ PM2_CNT

#define PM2_CNT   0x50

Definition at line 413 of file pch.h.

◆ PMBASE [1/2]

#define PMBASE   0x40

Definition at line 174 of file pch.h.

◆ PMBASE [2/2]

#define PMBASE   0x40

Definition at line 174 of file pch.h.

◆ PME_B0_EN

#define PME_B0_EN   (1 << 13)

Definition at line 425 of file pch.h.

◆ PME_B0_STS

#define PME_B0_STS   (1 << 13)

Definition at line 415 of file pch.h.

◆ PME_EN

#define PME_EN   (1 << 11)

Definition at line 426 of file pch.h.

◆ PME_STS

#define PME_STS   (1 << 11)

Definition at line 416 of file pch.h.

◆ PMIR

#define PMIR   0xac

Definition at line 98 of file pch.h.

◆ PRBTNOR_STS

#define PRBTNOR_STS   (1 << 11)

Definition at line 392 of file pch.h.

◆ PROC_CNT

#define PROC_CNT   0x10

Definition at line 409 of file pch.h.

◆ PRSTS

#define PRSTS   0x3310

Definition at line 306 of file pch.h.

◆ PSTS

#define PSTS   0x06

Definition at line 75 of file pch.h.

◆ PVC

#define PVC   0x000c /* 16bit */

Definition at line 179 of file pch.h.

◆ PVS

#define PVS   0x000e /* 16bit */

Definition at line 180 of file pch.h.

◆ PWRBTN_EN

#define PWRBTN_EN   (1 << 8)

Definition at line 401 of file pch.h.

◆ PWRBTN_STS

#define PWRBTN_STS   (1 << 8)

Definition at line 394 of file pch.h.

◆ RC

#define RC   0x3400 /* 32bit */

Definition at line 327 of file pch.h.

◆ RCTCL

#define RCTCL   0x0100 /* 32bit */

Definition at line 190 of file pch.h.

◆ RI_STS

#define RI_STS   (1 << 8)

Definition at line 419 of file pch.h.

◆ RMHWKCTL

#define RMHWKCTL   0x35b0 /* 32bit */

Definition at line 386 of file pch.h.

◆ RP1BA

#define RP1BA   0x0128 /* 64bit */

Definition at line 196 of file pch.h.

◆ RP1D

#define RP1D   0x0120 /* 32bit */

Definition at line 195 of file pch.h.

◆ RP2BA

#define RP2BA   0x0138 /* 64bit */

Definition at line 198 of file pch.h.

◆ RP2D

#define RP2D   0x0130 /* 32bit */

Definition at line 197 of file pch.h.

◆ RP3BA

#define RP3BA   0x0148 /* 64bit */

Definition at line 200 of file pch.h.

◆ RP3D

#define RP3D   0x0140 /* 32bit */

Definition at line 199 of file pch.h.

◆ RP4BA

#define RP4BA   0x0158 /* 64bit */

Definition at line 202 of file pch.h.

◆ RP4D

#define RP4D   0x0150 /* 32bit */

Definition at line 201 of file pch.h.

◆ RP5BA

#define RP5BA   0x0178 /* 64bit */

Definition at line 206 of file pch.h.

◆ RP5D

#define RP5D   0x0170 /* 32bit */

Definition at line 205 of file pch.h.

◆ RP6BA

#define RP6BA   0x0188 /* 64bit */

Definition at line 208 of file pch.h.

◆ RP6D

#define RP6D   0x0180 /* 32bit */

Definition at line 207 of file pch.h.

◆ RPC

#define RPC   0x0400 /* 32bit */

Definition at line 210 of file pch.h.

◆ RPFN

#define RPFN   0x0404 /* 32bit */

Definition at line 211 of file pch.h.

◆ RPFN_FNGET

#define RPFN_FNGET (   reg,
  port 
)    (((reg) >> ((port) * 4)) & 7)

Definition at line 216 of file pch.h.

◆ RPFN_FNMASK

#define RPFN_FNMASK (   port)    (7 << ((port) * 4))

Definition at line 220 of file pch.h.

◆ RPFN_FNSET

#define RPFN_FNSET (   port,
  func 
)    (((func) & 7) << ((port) * 4))

Definition at line 218 of file pch.h.

◆ RPFN_HIDE

#define RPFN_HIDE (   port)    (1 << (((port) * 4) + 3))

Definition at line 214 of file pch.h.

◆ RTC_BATTERY_DEAD

#define RTC_BATTERY_DEAD   (1 << 2)

Definition at line 101 of file pch.h.

◆ RTC_EN

#define RTC_EN   (1 << 10)

Definition at line 400 of file pch.h.

◆ RTC_POWER_FAILED

#define RTC_POWER_FAILED   (1 << 1)

Definition at line 102 of file pch.h.

◆ RTC_STS

#define RTC_STS   (1 << 10)

Definition at line 393 of file pch.h.

◆ SATA_IOBP_SP0G3IR

#define SATA_IOBP_SP0G3IR   0xea000151

Definition at line 157 of file pch.h.

◆ SATA_IOBP_SP1G3IR

#define SATA_IOBP_SP1G3IR   0xea000051

Definition at line 158 of file pch.h.

◆ SATA_SIRD

#define SATA_SIRD   0xa4 /* SATA Indexed Register Data */

Definition at line 153 of file pch.h.

◆ SATA_SIRI

#define SATA_SIRI   0xa0 /* SATA Indexed Register Index */

Definition at line 152 of file pch.h.

◆ SATA_SP

#define SATA_SP   0xd0 /* Scratchpad */

Definition at line 154 of file pch.h.

◆ SCI_EN

#define SCI_EN   (1 << 0)

Definition at line 407 of file pch.h.

◆ SECSTS

#define SECSTS   0x1e

Definition at line 77 of file pch.h.

◆ SERIRQ_CNTL

#define SERIRQ_CNTL   0x64

Definition at line 88 of file pch.h.

◆ SLEEP_AFTER_POWER_FAIL

#define SLEEP_AFTER_POWER_FAIL   (1 << 0)

Definition at line 103 of file pch.h.

◆ SLP_SMI_EN

#define SLP_SMI_EN   (1 << 4)

Definition at line 437 of file pch.h.

◆ SMB_BASE

#define SMB_BASE   0x20

Definition at line 162 of file pch.h.

◆ SMB_SMI_EN

#define SMB_SMI_EN   (1 << 1)

Definition at line 167 of file pch.h.

◆ SMB_WAK_STS

#define SMB_WAK_STS   (1 << 7)

Definition at line 420 of file pch.h.

◆ SMBUS_SLAVE_ADDR

#define SMBUS_SLAVE_ADDR   0x24

Definition at line 21 of file pch.h.

◆ SMI_EN

#define SMI_EN   0x30

Definition at line 428 of file pch.h.

◆ SMI_STS

#define SMI_STS   0x34

Definition at line 442 of file pch.h.

◆ SMLT

#define SMLT   0x1b

Definition at line 76 of file pch.h.

◆ SOFT_RESET_CTRL

#define SOFT_RESET_CTRL   0x38f4

Definition at line 303 of file pch.h.

◆ SOFT_RESET_DATA

#define SOFT_RESET_DATA   0x38f8

Definition at line 304 of file pch.h.

◆ SPIBAR_FADDR

#define SPIBAR_FADDR   0x3808 /* SPI flash address */

Definition at line 464 of file pch.h.

◆ SPIBAR_FDATA

#define SPIBAR_FDATA (   n)    (0x3810 + (4 * n)) /* SPI flash data */

Definition at line 465 of file pch.h.

◆ SPIBAR_HSFC

#define SPIBAR_HSFC   0x3806 /* SPI hardware sequence control */

Definition at line 458 of file pch.h.

◆ SPIBAR_HSFC_BYTE_COUNT

#define SPIBAR_HSFC_BYTE_COUNT (   c)    (((c - 1) & 0x3f) << 8)

Definition at line 459 of file pch.h.

◆ SPIBAR_HSFC_CYCLE_ERASE

#define SPIBAR_HSFC_CYCLE_ERASE   (3 << 1) /* Erase cycle */

Definition at line 462 of file pch.h.

◆ SPIBAR_HSFC_CYCLE_READ

#define SPIBAR_HSFC_CYCLE_READ   (0 << 1) /* Read cycle */

Definition at line 460 of file pch.h.

◆ SPIBAR_HSFC_CYCLE_WRITE

#define SPIBAR_HSFC_CYCLE_WRITE   (2 << 1) /* Write cycle */

Definition at line 461 of file pch.h.

◆ SPIBAR_HSFC_GO

#define SPIBAR_HSFC_GO   (1 << 0) /* GO: start SPI transaction */

Definition at line 463 of file pch.h.

◆ SPIBAR_HSFS

#define SPIBAR_HSFS   0x3804 /* SPI hardware sequence status */

Definition at line 453 of file pch.h.

◆ SPIBAR_HSFS_AEL

#define SPIBAR_HSFS_AEL   (1 << 2) /* SPI Access Error Log */

Definition at line 455 of file pch.h.

◆ SPIBAR_HSFS_FCERR

#define SPIBAR_HSFS_FCERR   (1 << 1) /* SPI Flash Cycle Error */

Definition at line 456 of file pch.h.

◆ SPIBAR_HSFS_FDONE

#define SPIBAR_HSFS_FDONE   (1 << 0) /* SPI Flash Cycle Done */

Definition at line 457 of file pch.h.

◆ SPIBAR_HSFS_SCIP

#define SPIBAR_HSFS_SCIP   (1 << 5) /* SPI Cycle In Progress */

Definition at line 454 of file pch.h.

◆ SS_CNT

#define SS_CNT   0x50

Definition at line 447 of file pch.h.

◆ SWGPE_STS

#define SWGPE_STS   (1 << 2)

Definition at line 422 of file pch.h.

◆ SWSMI_TMR_EN

#define SWSMI_TMR_EN   (1 << 6)

Definition at line 435 of file pch.h.

◆ TCO1_STS

#define TCO1_STS   0x64

Definition at line 449 of file pch.h.

◆ TCO2_STS

#define TCO2_STS   0x66

Definition at line 451 of file pch.h.

◆ TCO_EN

#define TCO_EN   (1 << 13)

Definition at line 432 of file pch.h.

◆ TCOSCI_EN

#define TCOSCI_EN   (1 << 6)

Definition at line 427 of file pch.h.

◆ TCOSCI_STS

#define TCOSCI_STS   (1 << 6)

Definition at line 421 of file pch.h.

◆ TCTL

#define TCTL   0x3000 /* 8bit */

Definition at line 231 of file pch.h.

◆ TMROF_EN

#define TMROF_EN   (1 << 0)

Definition at line 403 of file pch.h.

◆ TMROF_STS

#define TMROF_STS   (1 << 0)

Definition at line 397 of file pch.h.

◆ TRCR

#define TRCR   0x1e10 /* 64bit */

Definition at line 223 of file pch.h.

◆ TRSR

#define TRSR   0x1e00 /* 8bit */

Definition at line 222 of file pch.h.

◆ TWDR

#define TWDR   0x1e18 /* 64bit */

Definition at line 224 of file pch.h.

◆ ULBA

#define ULBA   0x0118 /* 64bit */

Definition at line 193 of file pch.h.

◆ ULD

#define ULD   0x0110 /* 32bit */

Definition at line 192 of file pch.h.

◆ UPRWC

#define UPRWC   0x3c

Definition at line 71 of file pch.h.

◆ UPRWC_WR_EN

#define UPRWC_WR_EN   (1 << 1) /* USB Per-Port Registers Write Enable */

Definition at line 72 of file pch.h.

◆ USBIR0

#define USBIR0   0x3500 /* 32bit */

Definition at line 359 of file pch.h.

◆ USBIR1

#define USBIR1   0x3504 /* 32bit */

Definition at line 360 of file pch.h.

◆ USBIR10

#define USBIR10   0x3528 /* 32bit */

Definition at line 369 of file pch.h.

◆ USBIR11

#define USBIR11   0x352c /* 32bit */

Definition at line 370 of file pch.h.

◆ USBIR12

#define USBIR12   0x3530 /* 32bit */

Definition at line 371 of file pch.h.

◆ USBIR13

#define USBIR13   0x3534 /* 32bit */

Definition at line 372 of file pch.h.

◆ USBIR2

#define USBIR2   0x3508 /* 32bit */

Definition at line 361 of file pch.h.

◆ USBIR3

#define USBIR3   0x350c /* 32bit */

Definition at line 362 of file pch.h.

◆ USBIR4

#define USBIR4   0x3510 /* 32bit */

Definition at line 363 of file pch.h.

◆ USBIR5

#define USBIR5   0x3514 /* 32bit */

Definition at line 364 of file pch.h.

◆ USBIR6

#define USBIR6   0x3518 /* 32bit */

Definition at line 365 of file pch.h.

◆ USBIR7

#define USBIR7   0x351c /* 32bit */

Definition at line 366 of file pch.h.

◆ USBIR8

#define USBIR8   0x3520 /* 32bit */

Definition at line 367 of file pch.h.

◆ USBIR9

#define USBIR9   0x3524 /* 32bit */

Definition at line 368 of file pch.h.

◆ USBIRA

#define USBIRA   0x3570 /* 32bit */

Definition at line 375 of file pch.h.

◆ USBIRB

#define USBIRB   0x357c /* 32bit */

Definition at line 376 of file pch.h.

◆ USBIRC

#define USBIRC   0x3564 /* 32bit */

Definition at line 374 of file pch.h.

◆ USBOCM1

#define USBOCM1   0x35a0 /* 32bit */

Definition at line 383 of file pch.h.

◆ USBOCM2

#define USBOCM2   0x35a4 /* 32bit */

Definition at line 384 of file pch.h.

◆ USBPDO

#define USBPDO   0x359c /* 32bit */

Definition at line 381 of file pch.h.

◆ V0CAP

#define V0CAP   0x0010 /* 32bit */

Definition at line 182 of file pch.h.

◆ V0CTL

#define V0CTL   0x0014 /* 32bit */

Definition at line 183 of file pch.h.

◆ V0STS

#define V0STS   0x001a /* 16bit */

Definition at line 184 of file pch.h.

◆ V1CAP

#define V1CAP   0x001c /* 32bit */

Definition at line 186 of file pch.h.

◆ V1CTL

#define V1CTL   0x0020 /* 32bit */

Definition at line 187 of file pch.h.

◆ V1STS

#define V1STS   0x0026 /* 16bit */

Definition at line 188 of file pch.h.

◆ VCAP1

#define VCAP1   0x0004 /* 32bit */

Definition at line 177 of file pch.h.

◆ VCAP2

#define VCAP2   0x0008 /* 32bit */

Definition at line 178 of file pch.h.

◆ VCH

#define VCH   0x0000 /* 32bit */

Definition at line 176 of file pch.h.

◆ WAK_STS

#define WAK_STS   (1 << 15)

Definition at line 390 of file pch.h.

Enumeration Type Documentation

◆ current_lookup_idx

enum current_lookup_idx
Enumerator
IF1_F57 
IF1_F5F 
IF1_753 
IF1_75F 
IF1_14B 
IF1_74B 
IF1_557 
IF1_757 
IF1_55F 
IF1_54B 

Definition at line 41 of file pch.h.

Function Documentation

◆ early_pch_init()

void early_pch_init ( void  )

Definition at line 299 of file early_pch.c.

◆ early_thermal_init()

void early_thermal_init ( void  )

Definition at line 14 of file early_thermal.c.

References msr_struct::lo, MSR_TEMPERATURE_TARGET, PCH_THERMAL_DEV, pci_and_config32(), PCI_DEV, pci_or_config32(), pci_read_config32(), pci_write_config32(), RCBA32_AND_OR, rdmsr(), read16(), read16p(), TBARB_TEMP, write16(), write16p(), and write8p().

Referenced by init_dram_ddr3(), and mainboard_romstage_entry().

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◆ early_usb_init()

void early_usb_init ( const struct southbridge_usb_port *  portmap)

Definition at line 11 of file early_usb.c.

References southbridge_usb_port::current, southbridge_usb_port::oc_pin, PCH_XHCI_DEV, pci_write_config32(), RCBA32, RCBA32_AND_OR, RCBA32_OR, read_pmbase16(), TOTAL_USB_PORTS, UPRWC, UPRWC_WR_EN, USBIR0, USBIRA, USBIRB, USBIRC, USBOCM1, USBOCM2, USBPDO, and write_pmbase16().

Referenced by early_pch_init(), and mainboard_romstage_entry().

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◆ enable_usb_bar()

void enable_usb_bar ( void  )

Definition at line 17 of file early_usb_mrc.c.

◆ ibexpeak_setup_bars()

void ibexpeak_setup_bars ( void  )

Definition at line 31 of file early_pch.c.

References ACPI_CNTL, ACPI_EN, BIOS_DEBUG, DEFAULT_HECIBAR, DEFAULT_PMBASE, GCS, inw(), outw(), PCH_LPC_DEV, PCI_BASE_ADDRESS_0, PCI_COMMAND, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, PCI_DEV, pci_write_config32(), pci_write_config8(), PMBASE, printk, RCBA, and RCBA32.

Referenced by ironlake_early_initialization().

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◆ pch_enable()

void pch_enable ( struct device *  dev)

Definition at line 404 of file pch.c.

◆ pch_iobp_update()

void pch_iobp_update ( u32  address,
u32  andvalue,
u32  orvalue 
)

Definition at line 86 of file pch.c.

◆ pch_setup_cir()

void pch_setup_cir ( int  chipset_type)

Definition at line 11 of file early_cir.c.

References BIOS_DEBUG, c, CIR10, CIR13, CIR14, CIR15, CIR16, CIR17, CIR18, CIR19, CIR20, CIR21, CIR22, CIR4, CIR6, CIR7, CIR8, CIR9, cpuid_eax(), die(), GCS, GEN_PMCON_1, GEN_PMCON_3, get_fms(), IRONLAKE_DESKTOP, PCH_LPC_DEV, PCI_DEVICE_ID, pci_or_config32(), pci_or_config8(), pci_read_config16(), pci_write_config32(), pci_write_config8(), PMIR, printk, RCBA32, RCBA32_AND_OR, RCBA32_OR, and RCBA8.

Referenced by early_pch_init().

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◆ southbridge_configure_default_intmap()

void southbridge_configure_default_intmap ( void  )

Definition at line 5 of file early_rcba.c.

References _none, D20IP, D20IP_XHCIIP, D20IR, D22IP, D22IP_MEI1IP, D22IR, D25IP, D25IP_LIP, D25IR, D26IP, D26IP_E2P, D26IR, D27IP, D27IP_ZIP, D27IR, D28IP, D28IP_P1IP, D28IP_P2IP, D28IP_P3IP, D28IP_P4IP, D28IP_P5IP, D28IP_P6IP, D28IP_P7IP, D28IP_P8IP, D28IR, D29IP, D29IP_E1P, D29IR, D31IP, D31IP_SIP, D31IP_SIP2, D31IP_SMIP, D31IP_TTIP, D31IR, DIR_ROUTE, INTA, INTB, INTC, INTD, OIC, PIRQA, PIRQB, PIRQC, PIRQD, RCBA16, RCBA32, and void().

Referenced by early_pch_init(), and mainboard_romstage_entry().

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Variable Documentation

◆ mainboard_usb_ports

const struct southbridge_usb_port mainboard_usb_ports[14]
extern

Definition at line 1 of file early_init.c.

Referenced by early_pch_init(), and mainboard_romstage_entry().