coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <stdint.h>
4 #include <device/pci_ops.h>
8 
10  /* Enabled, Current table lookup index, OC map */
11  { 1, IF1_557, 0 },
12  { 1, IF1_55F, 1 },
13  { 1, IF1_74B, 3 },
14  { 1, IF1_14B, 3 },
15  { 1, IF1_14B, 3 },
16  { 1, IF1_74B, 3 },
17  { 1, IF1_74B, 3 },
18  { 1, IF1_74B, 3 },
19  { 1, IF1_55F, 4 },
20  { 1, IF1_55F, 5 },
21  { 1, IF1_74B, 7 },
22  { 1, IF1_74B, 7 },
23  { 1, IF1_557, 7 },
24  { 1, IF1_55F, 7 },
25 };
26 
27 static void hybrid_graphics_init(void)
28 {
29  bool peg, igd;
30  u32 reg32;
31 
32  early_hybrid_graphics(&igd, &peg);
33 
34  /* Hide disabled devices */
35  reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN);
36  reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD);
37 
38  if (peg)
39  reg32 |= DEVEN_PEG10;
40 
41  if (igd)
42  reg32 |= DEVEN_IGD;
43  else
44  /* Disable IGD VGA decode, no GTT or GFX stolen */
45  pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);
46 
47  pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
48 }
49 
51 {
53 }
54 
55 void mainboard_get_spd_map(u8 *spd_addrmap)
56 {
57  spd_addrmap[0] = 0x50;
58  spd_addrmap[2] = 0x51;
59 }
__weak void mainboard_pre_raminit(struct romstage_params *params)
Definition: romstage.c:133
void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
Definition: romstage.c:17
#define GGC
Definition: host_bridge.h:9
#define DEVEN
Definition: host_bridge.h:16
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition: pci_ops.h:70
#define DEVEN_PEG10
Definition: host_bridge.h:11
#define DEVEN_IGD
Definition: host_bridge.h:10
static void hybrid_graphics_init(void)
Definition: romstage.c:27
void mainboard_get_spd_map(u8 *spd_addrmap)
Definition: romstage.c:55
const struct southbridge_usb_port mainboard_usb_ports[]
Definition: romstage.c:9
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
@ IF1_14B
Definition: pch.h:46
@ IF1_557
Definition: pch.h:48
@ IF1_74B
Definition: pch.h:47
@ IF1_55F
Definition: pch.h:50
uint32_t u32
Definition: stdint.h:51
uint8_t u8
Definition: stdint.h:45