coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
stdint.h
>
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#include <
device/pci_ops.h
>
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#include <
southbridge/intel/ibexpeak/pch.h
>
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#include <
drivers/lenovo/hybrid_graphics/hybrid_graphics.h
>
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#include <
northbridge/intel/ironlake/ironlake.h
>
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const
struct
southbridge_usb_port
mainboard_usb_ports
[] = {
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/* Enabled, Current table lookup index, OC map */
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{ 1,
IF1_557
, 0 },
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{ 1,
IF1_55F
, 1 },
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{ 1,
IF1_74B
, 3 },
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{ 1,
IF1_14B
, 3 },
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{ 1,
IF1_14B
, 3 },
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{ 1,
IF1_74B
, 3 },
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{ 1,
IF1_74B
, 3 },
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{ 1,
IF1_74B
, 3 },
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{ 1,
IF1_55F
, 4 },
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{ 1,
IF1_55F
, 5 },
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{ 1,
IF1_74B
, 7 },
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{ 1,
IF1_74B
, 7 },
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{ 1,
IF1_557
, 7 },
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{ 1,
IF1_55F
, 7 },
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};
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static
void
hybrid_graphics_init
(
void
)
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{
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bool
peg, igd;
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u32
reg32;
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early_hybrid_graphics
(&igd, &peg);
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/* Hide disabled devices */
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reg32 =
pci_read_config32
(
PCI_DEV
(0, 0, 0),
DEVEN
);
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reg32 &= ~(
DEVEN_PEG10
|
DEVEN_IGD
);
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if
(peg)
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reg32 |=
DEVEN_PEG10
;
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if
(igd)
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reg32 |=
DEVEN_IGD
;
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else
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/* Disable IGD VGA decode, no GTT or GFX stolen */
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pci_write_config16
(
PCI_DEV
(0, 0, 0),
GGC
, 2);
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pci_write_config32
(
PCI_DEV
(0, 0, 0),
DEVEN
, reg32);
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}
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void
mainboard_pre_raminit
(
void
)
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{
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hybrid_graphics_init
();
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}
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void
mainboard_get_spd_map
(
u8
*spd_addrmap)
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{
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spd_addrmap[0] = 0x50;
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spd_addrmap[2] = 0x51;
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}
mainboard_pre_raminit
__weak void mainboard_pre_raminit(struct romstage_params *params)
Definition:
romstage.c:133
early_hybrid_graphics
void early_hybrid_graphics(bool *enable_igd, bool *enable_peg)
Definition:
romstage.c:17
GGC
#define GGC
Definition:
host_bridge.h:9
DEVEN
#define DEVEN
Definition:
host_bridge.h:16
hybrid_graphics.h
pci_ops.h
pci_write_config32
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition:
pci_ops.h:76
pci_read_config32
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition:
pci_ops.h:58
pci_write_config16
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition:
pci_ops.h:70
DEVEN_PEG10
#define DEVEN_PEG10
Definition:
host_bridge.h:11
DEVEN_IGD
#define DEVEN_IGD
Definition:
host_bridge.h:10
ironlake.h
hybrid_graphics_init
static void hybrid_graphics_init(void)
Definition:
romstage.c:27
mainboard_get_spd_map
void mainboard_get_spd_map(u8 *spd_addrmap)
Definition:
romstage.c:55
mainboard_usb_ports
const struct southbridge_usb_port mainboard_usb_ports[]
Definition:
romstage.c:9
PCI_DEV
#define PCI_DEV(SEGBUS, DEV, FN)
Definition:
pci_type.h:14
pch.h
IF1_14B
@ IF1_14B
Definition:
pch.h:46
IF1_557
@ IF1_557
Definition:
pch.h:48
IF1_74B
@ IF1_74B
Definition:
pch.h:47
IF1_55F
@ IF1_55F
Definition:
pch.h:50
stdint.h
u32
uint32_t u32
Definition:
stdint.h:51
u8
uint8_t u8
Definition:
stdint.h:45
southbridge_usb_port
Definition:
pch.h:56
src
mainboard
lenovo
t410
romstage.c
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