coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
usb_debug.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 // Use simple device model for this file even in ramstage
4 #define __SIMPLE_DEVICE__
5 
6 #include <stdint.h>
7 #include <device/pci_ops.h>
8 #include <device/pci_ehci.h>
9 #include <device/pci_def.h>
10 
11 pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
12 {
13  u32 class;
14  pci_devfn_t dev;
15 
16  if (!CONFIG(HAVE_USBDEBUG_OPTIONS))
17  return PCI_DEV(0, 0x1d, 7);
18 
19  if (hcd_idx == 2)
20  dev = PCI_DEV(0, 0x1a, 0);
21  else
22  dev = PCI_DEV(0, 0x1d, 0);
23 
24  /* If we enter here before RCBA programming, EHCI function may
25  * appear with the highest function number instead.
26  */
27  class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
28  if (class != PCI_EHCI_CLASSCODE)
29  dev |= PCI_DEV(0, 0, 7);
30 
31  return dev;
32 }
33 
34 /* Required for successful build, but currently empty. */
35 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
36 {
37  /* Not needed, the ICH* southbridges hardcode physical USB port 1. */
38 }
@ CONFIG
Definition: dsi_common.h:201
port
Definition: i915.h:29
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
#define PCI_CLASS_REVISION
Definition: pci_def.h:40
#define PCI_EHCI_CLASSCODE
Definition: pci_ehci.h:11
#define PCI_DEV(SEGBUS, DEV, FN)
Definition: pci_type.h:14
u32 pci_devfn_t
Definition: pci_type.h:8
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
Definition: usb_debug.c:9
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
Definition: usb_debug.c:14
uint32_t u32
Definition: stdint.h:51