coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <stdint.h>
4 #include <string.h>
5 #include <cbfs.h>
6 #include <device/pci_ops.h>
7 #include <console/console.h>
11 #include "ec.h"
12 
13 #define SPD_LEN 256
14 
16 {
17  /* Memory map KB9012 EC registers */
20  CONFIG_EC_BASE_ADDRESS | 1);
22 
23  /* Enable external USB port power. */
24  if (CONFIG(USBDEBUG))
25  ec_mm_set_bit(0x3b, 4);
26 }
27 
29  { 1, 1, 0 },
30  { 1, 0, 0 },
31  { 1, 1, 1 },
32  { 1, 0, 1 },
33  { 1, 1, 2 },
34  { 1, 0, 2 },
35  { 0, 0, 3 },
36  { 0, 1, 3 },
37  { 1, 0, 4 },
38  { 1, 1, 4 },
39  { 1, 1, 5 },
40  { 1, 1, 5 },
41  { 1, 1, 6 },
42  { 1, 1, 6 },
43 };
44 
45 static const char *mainboard_spd_names[9] = {
46  "ELPIDA 4GB",
47  "SAMSUNG 4GB",
48  "HYNIX 4GB",
49  "ELPIDA 8GB",
50  "SAMSUNG 8GB",
51  "HYNIX 8GB",
52  "ELPIDA 2GB",
53  "SAMSUNG 2GB",
54  "HYNIX 2GB",
55 };
56 
57 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
58 {
59  void *spd_file;
60  size_t spd_file_len = 0;
61  const int spd_gpios[] = {71, 70, 16, 48, -1};
62 
63  u32 spd_index = get_gpios(spd_gpios);
65  /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */
66  spd_index = 6;
67  }
68 
69  printk(BIOS_INFO, "SPD index %d (%s)\n",
71 
72  /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */
73  spd_file = cbfs_map("spd.bin", &spd_file_len);
74 
75  if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN)
76  die("SPD data not found.");
77 
78  memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN);
79 }
void * memcpy(void *dest, const void *src, size_t n)
Definition: memcpy.c:7
#define ARRAY_SIZE(a)
Definition: helpers.h:12
static void * cbfs_map(const char *name, size_t *size_out)
Definition: cbfs.h:246
#define printk(level,...)
Definition: stdlib.h:16
void __noreturn die(const char *fmt,...)
Definition: die.c:17
@ CONFIG
Definition: dsi_common.h:201
u8 spd_raw_data[256]
Definition: ddr3.h:156
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
Definition: pci_ops.h:70
#define BIOS_INFO
BIOS_INFO - Expected events.
Definition: loglevel.h:113
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition: early_init.c:25
const struct southbridge_usb_port mainboard_usb_ports[]
Definition: early_init.c:8
static const int spd_index[32]
Definition: memory.c:10
#define SPD_LEN
Definition: early_init.c:13
static const char * mainboard_spd_names[9]
Definition: early_init.c:45
#define ec_mm_set_bit(addr, bit)
Definition: ec.h:11
#define LGMR
Definition: espi.h:29
#define PCH_LPC_DEV
Definition: lpc.h:7
#define BIOS_DEC_EN1
Definition: pch.h:155
unsigned int get_gpios(const int *gpio_num_array)
Definition: gpio.c:107
uint32_t u32
Definition: stdint.h:51