clock.h File Reference

#include <arch/hlt.h>
#include <console/console.h>
#include <device/mmio.h>
#include <soc/clk_rst.h>
#include <stdint.h>

Include dependency graph for clock.h:

Go to the source code of this file.

Macros
#define	CLK_SRC_DEV_ID(dev, src)   CLK_SRC_##dev##_##src
#define	CLK_SRC_FREQ_ID(dev, src)   CLK_SRC_FREQ_##dev##_##src
#define	CLK_SRC_DEVICE(dev, a, b, c, d, e, f, g, h)
#define	CLOCK_PLL_STABLE_DELAY_US   300
#define	IO_STABILIZATION_DELAY   (2)
#define	LOGIC_STABILIZATION_DELAY   (2)
#define	CLK_DIVIDER(REF, FREQ)   (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)
#define	CLK_FREQUENCY(REF, REG)   (((REF) * 2) / ((REG) + 2))
#define	get_i2c_clk_div(src, freq)    (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1)
#define	get_clk_div(src, freq)   CLK_DIVIDER(src,freq)
#define	CLK_DIV_MASK   0xff
#define	CLK_DIV_MASK_I2C   0xffff
#define	clock_configure_source(device, src, freq)
#define	TEGRA_CLK_M_KHZ   (clock_get_osc_khz()/2)
#define	TEGRA_PLLX_KHZ   CONFIG_PLLX_KHZ
#define	TEGRA_PLLP_KHZ   (408000)
#define	TEGRA_PLLP_OUT3_KHZ   (68000)
#define	TEGRA_PLLC_KHZ   (600000)
#define	TEGRA_PLLD_KHZ   (925000)
#define	TEGRA_PLLD_OUT0_KHZ   (TEGRA_PLLD_KHZ/2)
#define	TEGRA_PLLU_KHZ   (960000)
#define	clock_enable(l, h, u, v, w, x, y)
#define	clock_disable(l, h, u, v, w, x, y)
#define	clock_set_reset(l, h, u, v, w, x, y)
#define	clock_clr_reset(l, h, u, v, w, x, y)
#define	clock_enable_l(l)   clock_enable(l, 0, 0, 0, 0, 0, 0)
#define	clock_enable_h(h)   clock_enable(0, h, 0, 0, 0, 0, 0)
#define	clock_enable_u(u)   clock_enable(0, 0, u, 0, 0, 0, 0)
#define	clock_enable_v(v)   clock_enable(0, 0, 0, v, 0, 0, 0)
#define	clock_enable_w(w)   clock_enable(0, 0, 0, 0, w, 0, 0)
#define	clock_enable_x(x)   clock_enable(0, 0, 0, 0, 0, x, 0)
#define	clock_enable_y(y)   clock_enable(0, 0, 0, 0, 0, 0, y)
#define	clock_disable_l(l)   clock_disable(l, 0, 0, 0, 0, 0, 0)
#define	clock_disable_h(h)   clock_disable(0, h, 0, 0, 0, 0, 0)
#define	clock_disable_u(u)   clock_disable(0, 0, u, 0, 0, 0, 0)
#define	clock_disable_v(v)   clock_disable(0, 0, 0, v, 0, 0, 0)
#define	clock_disable_w(w)   clock_disable(0, 0, 0, 0, w, 0, 0)
#define	clock_disable_x(x)   clock_disable(0, 0, 0, 0, 0, x, 0)
#define	clock_disable_y(y)   clock_disable(0, 0, 0, 0, 0, 0, y)
#define	clock_set_reset_l(l)   clock_set_reset(l, 0, 0, 0, 0, 0, 0)
#define	clock_set_reset_h(h)   clock_set_reset(0, h, 0, 0, 0, 0, 0)
#define	clock_set_reset_u(u)   clock_set_reset(0, 0, u, 0, 0, 0, 0)
#define	clock_set_reset_v(v)   clock_set_reset(0, 0, 0, v, 0, 0, 0)
#define	clock_set_reset_w(w)   clock_set_reset(0, 0, 0, 0, w, 0, 0)
#define	clock_set_reset_x(x)   clock_set_reset(0, 0, 0, 0, 0, x, 0)
#define	clock_set_reset_y(x)   clock_set_reset(0, 0, 0, 0, 0, y, 0)
#define	clock_clr_reset_l(l)   clock_clr_reset(l, 0, 0, 0, 0, 0, 0)
#define	clock_clr_reset_h(h)   clock_clr_reset(0, h, 0, 0, 0, 0, 0)
#define	clock_clr_reset_u(u)   clock_clr_reset(0, 0, u, 0, 0, 0, 0)
#define	clock_clr_reset_v(v)   clock_clr_reset(0, 0, 0, v, 0, 0, 0)
#define	clock_clr_reset_w(w)   clock_clr_reset(0, 0, 0, 0, w, 0, 0)
#define	clock_clr_reset_x(x)   clock_clr_reset(0, 0, 0, 0, 0, x, 0)
#define	clock_clr_reset_y(y)   clock_clr_reset(0, 0, 0, 0, 0, 0, y)
#define	clock_enable_clear_reset_l(l)    clock_enable_clear_reset(l, 0, 0, 0, 0, 0, 0)
#define	clock_enable_clear_reset_h(h)    clock_enable_clear_reset(0, h, 0, 0, 0, 0, 0)
#define	clock_enable_clear_reset_u(u)    clock_enable_clear_reset(0, 0, u, 0, 0, 0, 0)
#define	clock_enable_clear_reset_v(v)    clock_enable_clear_reset(0, 0, 0, v, 0, 0, 0)
#define	clock_enable_clear_reset_w(w)    clock_enable_clear_reset(0, 0, 0, 0, w, 0, 0)
#define	clock_enable_clear_reset_x(x)    clock_enable_clear_reset(0, 0, 0, 0, 0, x, 0)
#define	clock_enable_clear_reset_y(y)    clock_enable_clear_reset(0, 0, 0, 0, 0, 0, y)

Enumerations
enum	{   CLK_L_CPU = 0x1 << 0 , CLK_L_COP = 0x1 << 1 , CLK_L_TRIG_SYS = 0x1 << 2 , CLK_L_RTC = 0x1 << 4 ,   CLK_L_TMR = 0x1 << 5 , CLK_L_UARTA = 0x1 << 6 , CLK_L_UARTB = 0x1 << 7 , CLK_L_GPIO = 0x1 << 8 ,   CLK_L_SDMMC2 = 0x1 << 9 , CLK_L_SPDIF = 0x1 << 10 , CLK_L_I2S2 = 0x1 << 11 , CLK_L_I2C1 = 0x1 << 12 ,   CLK_L_NDFLASH = 0x1 << 13 , CLK_L_SDMMC1 = 0x1 << 14 , CLK_L_SDMMC4 = 0x1 << 15 , CLK_L_PWM = 0x1 << 17 ,   CLK_L_I2S3 = 0x1 << 18 , CLK_L_EPP = 0x1 << 19 , CLK_L_VI = 0x1 << 20 , CLK_L_2D = 0x1 << 21 ,   CLK_L_USBD = 0x1 << 22 , CLK_L_ISP = 0x1 << 23 , CLK_L_3D = 0x1 << 24 , CLK_L_DISP2 = 0x1 << 26 ,   CLK_L_DISP1 = 0x1 << 27 , CLK_L_HOST1X = 0x1 << 28 , CLK_L_VCP = 0x1 << 29 , CLK_L_I2S1 = 0x1 << 30 ,   CLK_L_CACHE2 = 0x1 << 31 , CLK_H_MEM = 0x1 << 0 , CLK_H_AHBDMA = 0x1 << 1 , CLK_H_APBDMA = 0x1 << 2 ,   CLK_H_KBC = 0x1 << 4 , CLK_H_STAT_MON = 0x1 << 5 , CLK_H_PMC = 0x1 << 6 , CLK_H_FUSE = 0x1 << 7 ,   CLK_H_KFUSE = 0x1 << 8 , CLK_H_SBC1 = 0x1 << 9 , CLK_H_SNOR = 0x1 << 10 , CLK_H_JTAG2TBC = 0x1 << 11 ,   CLK_H_SBC2 = 0x1 << 12 , CLK_H_SBC3 = 0x1 << 14 , CLK_H_I2C5 = 0x1 << 15 , CLK_H_DSI = 0x1 << 16 ,   CLK_H_HSI = 0x1 << 18 , CLK_H_HDMI = 0x1 << 19 , CLK_H_CSI = 0x1 << 20 , CLK_H_I2C2 = 0x1 << 22 ,   CLK_H_UARTC = 0x1 << 23 , CLK_H_MIPI_CAL = 0x1 << 24 , CLK_H_EMC = 0x1 << 25 , CLK_H_USB2 = 0x1 << 26 ,   CLK_H_USB3 = 0x1 << 27 , CLK_H_MPE = 0x1 << 28 , CLK_H_VDE = 0x1 << 29 , CLK_H_BSEA = 0x1 << 30 ,   CLK_H_BSEV = 0x1 << 31 , CLK_U_UARTD = 0x1 << 1 , CLK_U_UARTE = 0x1 << 2 , CLK_U_I2C3 = 0x1 << 3 ,   CLK_U_SBC4 = 0x1 << 4 , CLK_U_SDMMC3 = 0x1 << 5 , CLK_U_PCIE = 0x1 << 6 , CLK_U_OWR = 0x1 << 7 ,   CLK_U_AFI = 0x1 << 8 , CLK_U_CSITE = 0x1 << 9 , CLK_U_PCIEXCLK = 0x1 << 10 , CLK_U_AVPUCQ = 0x1 << 11 ,   CLK_U_TRACECLKIN = 0x1 << 13 , CLK_U_SOC_THERM = 0x1 << 14 , CLK_U_DTV = 0x1 << 15 , CLK_U_NAND_SPEED = 0x1 << 16 ,   CLK_U_I2C_SLOW = 0x1 << 17 , CLK_U_DSIB = 0x1 << 18 , CLK_U_TSEC = 0x1 << 19 , CLK_U_IRAMA = 0x1 << 20 ,   CLK_U_IRAMB = 0x1 << 21 , CLK_U_IRAMC = 0x1 << 22 , CLK_U_EMUCIF = 0x1 << 23 , CLK_U_IRAMD = 0x1 << 23 ,   CLK_U_CRAM2 = 0x2 << 24 , CLK_U_XUSB_HOST = 0x1 << 25 , CLK_U_MSENC = 0x1 << 27 , CLK_U_SUS_OUT = 0x1 << 28 ,   CLK_U_DEV2_OUT = 0x1 << 29 , CLK_U_DEV1_OUT = 0x1 << 30 , CLK_U_XUSB_DEV = 0x1 << 31 , CLK_V_CPUG = 0x1 << 0 ,   CLK_V_CPULP = 0x1 << 1 , CLK_V_3D2 = 0x1 << 2 , CLK_V_MSELECT = 0x1 << 3 , CLK_V_I2S4 = 0x1 << 5 ,   CLK_V_I2S5 = 0x1 << 6 , CLK_V_I2C4 = 0x1 << 7 , CLK_V_SBC5 = 0x1 << 8 , CLK_V_SBC6 = 0x1 << 9 ,   CLK_V_AHUB = 0x1 << 10 , CLK_V_APB2APE = 0x1 << 11 , CLK_V_HDA2CODEC_2X = 0x1 << 15 , CLK_V_ATOMICS = 0x1 << 16 ,   CLK_V_ACTMON = 0x1 << 23 , CLK_V_EXTPERIPH1 = 0x1 << 24 , CLK_V_SATA = 0x1 << 28 , CLK_V_HDA = 0x1 << 29 ,   CLK_W_HDA2HDMICODEC = 0x1 << 0 , CLK_W_SATACOLD = 0x1 << 1 , CLK_W_CEC = 0x1 << 8 , CLK_W_XUSB_PADCTL = 0x1 << 14 ,   CLK_W_ENTROPY = 0x1 << 21 , CLK_W_DVFS = 0x1 << 27 , CLK_W_XUSB_SS = 0x1 << 28 , CLK_X_GPU = 0x1 << 24 ,   CLK_X_SOR1 = 0x1 << 23 , CLK_X_SOR0 = 0x1 << 22 , CLK_X_DPAUX = 0x1 << 21 , CLK_X_VIC = 0x1 << 18 ,   CLK_X_UART_FST_MIPI_CAL = 0x1 << 17 , CLK_X_MIPIBIF = 0x1 << 13 , CLK_X_I2C6 = 0x1 << 6 , CLK_X_ETR = 0x1 << 3 ,   CLK_X_SPARE = 0x1 << 0 , CLK_Y_APE = 0x1 << 6 , CLK_Y_DPAUX1 = 0x1 << 15 , CLK_Y_QSPI = 0x1 << 19 ,   CLK_Y_SOR_SAFE = 0x1 << 30 }
enum	{   PLLP = 0 , PLLC2 = 1 , PLLC = 2 , PLLC_OUT1 = 3 ,   PLLM = 4 , CLK_M = 5 , CLK_S = 6 , PLLE = 7 ,   PLLA = 8 , PLLD = 9 , PLLD2 = 10 , PLLC4_OUT0 = 11 ,   PLLC4_OUT1 = 12 , PLLC4_OUT2 = 13 , PLLC4_OUT3 = 14 , PLLC4_OUT0_L = 15 ,   PLLC4_OUT1_L = 16 , PLLC4_OUT2_L = 17 , PLLD_OUT0 = 18 , PLLP_OUT3 = 19 ,   PLLC2_OUT0 = 20 , UNUSED0 = 100 , UNUSED1 = 101 , UNUSED2 = 102 ,   UNUSED3 = 103 , UNUSED4 = 104 , UNUSED5 = 105 , UNUSED6 = 106 ,   UNUSED7 = 107 }
enum	{   CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE ,   CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE ,   CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE ,   CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE ,   CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE , CLK_SRC_DEVICE ,   CLK_SRC_DEVICE , CLK_SRC_DEVICE }

Functions
static void	_clock_set_div (u32 *reg, const char *name, u32 div, u32 div_mask, u32 src)
int	clock_get_osc_khz (void)
int	clock_get_pll_input_khz (void)
u32	clock_configure_plld (u32 frequency)
void	clock_early_uart (void)
void	clock_external_output (int clk_id)
void	clock_sdram (u32 m, u32 n, u32 p, u32 setup, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq)
void	clock_cpu0_config (void)
void	clock_halt_avp (void)
void	clock_enable_regs (u32 bits[DEV_CONFIG_BLOCKS])
void	clock_disable_regs (u32 bits[DEV_CONFIG_BLOCKS])
void	clock_set_reset_regs (u32 bits[DEV_CONFIG_BLOCKS])
void	clock_clr_reset_regs (u32 bits[DEV_CONFIG_BLOCKS])
void	clock_enable_clear_reset (u32 l, u32 h, u32 u, u32 v, u32 w, u32 x, u32 y)
void	clock_grp_enable_clear_reset (u32 val, u32 *clk_enb_set_reg, u32 *rst_dev_clr_reg)
void	clock_reset_l (u32 l)
void	clock_reset_h (u32 h)
void	clock_reset_u (u32 u)
void	clock_reset_v (u32 v)
void	clock_reset_w (u32 w)
void	clock_reset_x (u32 x)
void	clock_reset_y (u32 y)
void	clock_init (void)
void	clock_init_arm_generic_timer (void)
void	sor_clock_stop (void)
void	sor_clock_start (void)
void	clock_enable_audio (void)

Macro Definition Documentation

CLK_DIV_MASK

#define CLK_DIV_MASK   0xff

Definition at line 315 of file clock.h.

CLK_DIV_MASK_I2C

#define CLK_DIV_MASK_I2C   0xffff

Definition at line 316 of file clock.h.

CLK_DIVIDER

#define CLK_DIVIDER	(		REF,
			FREQ
	)		(DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)

Definition at line 277 of file clock.h.

CLK_FREQUENCY

#define CLK_FREQUENCY	(		REF,
			REG
	)		(((REF) * 2) / ((REG) + 2))

Definition at line 296 of file clock.h.

CLK_SRC_DEV_ID

#define CLK_SRC_DEV_ID	(		dev,
			src
	)		CLK_SRC_##dev##_##src

Definition at line 182 of file clock.h.

CLK_SRC_DEVICE

#define CLK_SRC_DEVICE	(		dev,
			a,
			b,
			c,
			d,
			e,
			f,
			g,
			h
	)

Value:

        CLK_SRC_DEV_ID(dev, a) = 0,              \
        CLK_SRC_DEV_ID(dev, b) = 1,              \
        CLK_SRC_DEV_ID(dev, c) = 2,              \
        CLK_SRC_DEV_ID(dev, d) = 3,              \
        CLK_SRC_DEV_ID(dev, e) = 4,              \
        CLK_SRC_DEV_ID(dev, f) = 5,              \
        CLK_SRC_DEV_ID(dev, g) = 6,              \
        CLK_SRC_DEV_ID(dev, h) = 7,              \
        CLK_SRC_FREQ_ID(dev, a) = a,             \
        CLK_SRC_FREQ_ID(dev, b) = b,             \
        CLK_SRC_FREQ_ID(dev, c) = c,             \
        CLK_SRC_FREQ_ID(dev, d) = d,             \
        CLK_SRC_FREQ_ID(dev, e) = e,             \
        CLK_SRC_FREQ_ID(dev, f) = f,             \
        CLK_SRC_FREQ_ID(dev, g) = g,             \
        CLK_SRC_FREQ_ID(dev, h) = h

Definition at line 185 of file clock.h.

CLK_SRC_FREQ_ID

#define CLK_SRC_FREQ_ID	(		dev,
			src
	)		CLK_SRC_FREQ_##dev##_##src

Definition at line 183 of file clock.h.

clock_clr_reset

#define clock_clr_reset	(		l,
			h,
			u,
			v,
			w,
			x,
			y
	)

Value:

        do {                                                            \
                u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y};    \
                clock_clr_reset_regs(bits);                             \
        } while (0)

Definition at line 351 of file clock.h.

clock_clr_reset_h

#define clock_clr_reset_h

(

h

)

clock_clr_reset(0, h, 0, 0, 0, 0, 0)

Definition at line 382 of file clock.h.

clock_clr_reset_l

#define clock_clr_reset_l

(

l

)

clock_clr_reset(l, 0, 0, 0, 0, 0, 0)

Definition at line 381 of file clock.h.

clock_clr_reset_u

#define clock_clr_reset_u

(

u

)

clock_clr_reset(0, 0, u, 0, 0, 0, 0)

Definition at line 383 of file clock.h.

clock_clr_reset_v

#define clock_clr_reset_v

(

v

)

clock_clr_reset(0, 0, 0, v, 0, 0, 0)

Definition at line 384 of file clock.h.

clock_clr_reset_w

#define clock_clr_reset_w

(

w

)

clock_clr_reset(0, 0, 0, 0, w, 0, 0)

Definition at line 385 of file clock.h.

clock_clr_reset_x

#define clock_clr_reset_x

(

x

)

clock_clr_reset(0, 0, 0, 0, 0, x, 0)

Definition at line 386 of file clock.h.

clock_clr_reset_y

#define clock_clr_reset_y

(

y

)

clock_clr_reset(0, 0, 0, 0, 0, 0, y)

Definition at line 387 of file clock.h.

clock_configure_source

#define clock_configure_source	(		device,
			src,
			freq
	)

Value:

        _clock_set_div(CLK_RST_REG(clk_src_##device), #device,          \
                       get_clk_div(TEGRA_##src##_KHZ, freq), CLK_DIV_MASK, \
                       CLK_SRC_DEV_ID(device, src))

Definition at line 318 of file clock.h.

clock_disable

#define clock_disable	(		l,
			h,
			u,
			v,
			w,
			x,
			y
	)

Value:

        do {                                                            \
                u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y};    \
                clock_disable_regs(bits);                               \
        } while (0)

Definition at line 339 of file clock.h.

clock_disable_h

#define clock_disable_h

(

h

)

clock_disable(0, h, 0, 0, 0, 0, 0)

Definition at line 366 of file clock.h.

clock_disable_l

#define clock_disable_l

(

l

)

clock_disable(l, 0, 0, 0, 0, 0, 0)

Definition at line 365 of file clock.h.

clock_disable_u

#define clock_disable_u

(

u

)

clock_disable(0, 0, u, 0, 0, 0, 0)

Definition at line 367 of file clock.h.

clock_disable_v

#define clock_disable_v

(

v

)

clock_disable(0, 0, 0, v, 0, 0, 0)

Definition at line 368 of file clock.h.

clock_disable_w

#define clock_disable_w

(

w

)

clock_disable(0, 0, 0, 0, w, 0, 0)

Definition at line 369 of file clock.h.

clock_disable_x

#define clock_disable_x

(

x

)

clock_disable(0, 0, 0, 0, 0, x, 0)

Definition at line 370 of file clock.h.

clock_disable_y

#define clock_disable_y

(

y

)

clock_disable(0, 0, 0, 0, 0, 0, y)

Definition at line 371 of file clock.h.

clock_enable

#define clock_enable	(		l,
			h,
			u,
			v,
			w,
			x,
			y
	)

Value:

        do {                                                            \
                u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y};    \
                clock_enable_regs(bits);                                \
        } while (0)

Definition at line 333 of file clock.h.

clock_enable_clear_reset_h

#define clock_enable_clear_reset_h

(

h

)

clock_enable_clear_reset(0, h, 0, 0, 0, 0, 0)

Definition at line 391 of file clock.h.

clock_enable_clear_reset_l

#define clock_enable_clear_reset_l

(

l

)

clock_enable_clear_reset(l, 0, 0, 0, 0, 0, 0)

Definition at line 389 of file clock.h.

clock_enable_clear_reset_u

#define clock_enable_clear_reset_u

(

u

)

clock_enable_clear_reset(0, 0, u, 0, 0, 0, 0)

Definition at line 393 of file clock.h.

clock_enable_clear_reset_v

#define clock_enable_clear_reset_v

(

v

)

clock_enable_clear_reset(0, 0, 0, v, 0, 0, 0)

Definition at line 395 of file clock.h.

clock_enable_clear_reset_w

#define clock_enable_clear_reset_w

(

w

)

clock_enable_clear_reset(0, 0, 0, 0, w, 0, 0)

Definition at line 397 of file clock.h.

clock_enable_clear_reset_x

#define clock_enable_clear_reset_x

(

x

)

clock_enable_clear_reset(0, 0, 0, 0, 0, x, 0)

Definition at line 399 of file clock.h.

clock_enable_clear_reset_y

#define clock_enable_clear_reset_y

(

y

)

clock_enable_clear_reset(0, 0, 0, 0, 0, 0, y)

Definition at line 401 of file clock.h.

clock_enable_h

#define clock_enable_h

(

h

)

clock_enable(0, h, 0, 0, 0, 0, 0)

Definition at line 358 of file clock.h.

clock_enable_l

#define clock_enable_l

(

l

)

clock_enable(l, 0, 0, 0, 0, 0, 0)

Definition at line 357 of file clock.h.

clock_enable_u

#define clock_enable_u

(

u

)

clock_enable(0, 0, u, 0, 0, 0, 0)

Definition at line 359 of file clock.h.

clock_enable_v

#define clock_enable_v

(

v

)

clock_enable(0, 0, 0, v, 0, 0, 0)

Definition at line 360 of file clock.h.

clock_enable_w

#define clock_enable_w

(

w

)

clock_enable(0, 0, 0, 0, w, 0, 0)

Definition at line 361 of file clock.h.

clock_enable_x

#define clock_enable_x

(

x

)

clock_enable(0, 0, 0, 0, 0, x, 0)

Definition at line 362 of file clock.h.

clock_enable_y

#define clock_enable_y

(

y

)

clock_enable(0, 0, 0, 0, 0, 0, y)

Definition at line 363 of file clock.h.

CLOCK_PLL_STABLE_DELAY_US

#define CLOCK_PLL_STABLE_DELAY_US   300

Definition at line 251 of file clock.h.

clock_set_reset

#define clock_set_reset	(		l,
			h,
			u,
			v,
			w,
			x,
			y
	)

Value:

        do {                                                            \
                u32 bits[DEV_CONFIG_BLOCKS] = {l, h, u, v, w, x, y};    \
                clock_set_reset_regs(bits);                             \
        } while (0)

Definition at line 345 of file clock.h.

clock_set_reset_h

#define clock_set_reset_h

(

h

)

clock_set_reset(0, h, 0, 0, 0, 0, 0)

Definition at line 374 of file clock.h.

clock_set_reset_l

#define clock_set_reset_l

(

l

)

clock_set_reset(l, 0, 0, 0, 0, 0, 0)

Definition at line 373 of file clock.h.

clock_set_reset_u

#define clock_set_reset_u

(

u

)

clock_set_reset(0, 0, u, 0, 0, 0, 0)

Definition at line 375 of file clock.h.

clock_set_reset_v

#define clock_set_reset_v

(

v

)

clock_set_reset(0, 0, 0, v, 0, 0, 0)

Definition at line 376 of file clock.h.

clock_set_reset_w

#define clock_set_reset_w

(

w

)

clock_set_reset(0, 0, 0, 0, w, 0, 0)

Definition at line 377 of file clock.h.

clock_set_reset_x

#define clock_set_reset_x

(

x

)

clock_set_reset(0, 0, 0, 0, 0, x, 0)

Definition at line 378 of file clock.h.

clock_set_reset_y

#define clock_set_reset_y

(

x

)

clock_set_reset(0, 0, 0, 0, 0, y, 0)

Definition at line 379 of file clock.h.

get_clk_div

#define get_clk_div	(		src,
			freq
	)		CLK_DIVIDER(src,freq)

Definition at line 314 of file clock.h.

get_i2c_clk_div

#define get_i2c_clk_div	(		src,
			freq
	)		(DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1)

Definition at line 312 of file clock.h.

IO_STABILIZATION_DELAY

#define IO_STABILIZATION_DELAY   (2)

Definition at line 253 of file clock.h.

LOGIC_STABILIZATION_DELAY

#define LOGIC_STABILIZATION_DELAY   (2)

Definition at line 254 of file clock.h.

TEGRA_CLK_M_KHZ

#define TEGRA_CLK_M_KHZ   (clock_get_osc_khz()/2)

Definition at line 324 of file clock.h.

TEGRA_PLLC_KHZ

#define TEGRA_PLLC_KHZ   (600000)

Definition at line 328 of file clock.h.

TEGRA_PLLD_KHZ

#define TEGRA_PLLD_KHZ   (925000)

Definition at line 329 of file clock.h.

TEGRA_PLLD_OUT0_KHZ

#define TEGRA_PLLD_OUT0_KHZ   (TEGRA_PLLD_KHZ/2)

Definition at line 330 of file clock.h.

TEGRA_PLLP_KHZ

#define TEGRA_PLLP_KHZ   (408000)

Definition at line 326 of file clock.h.

TEGRA_PLLP_OUT3_KHZ

#define TEGRA_PLLP_OUT3_KHZ   (68000)

Definition at line 327 of file clock.h.

TEGRA_PLLU_KHZ

#define TEGRA_PLLU_KHZ   (960000)

Definition at line 331 of file clock.h.

TEGRA_PLLX_KHZ

#define TEGRA_PLLX_KHZ   CONFIG_PLLX_KHZ

Definition at line 325 of file clock.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
CLK_L_CPU
CLK_L_COP
CLK_L_TRIG_SYS
CLK_L_RTC
CLK_L_TMR
CLK_L_UARTA
CLK_L_UARTB
CLK_L_GPIO
CLK_L_SDMMC2
CLK_L_SPDIF
CLK_L_I2S2
CLK_L_I2C1
CLK_L_NDFLASH
CLK_L_SDMMC1
CLK_L_SDMMC4
CLK_L_PWM
CLK_L_I2S3
CLK_L_EPP
CLK_L_VI
CLK_L_2D
CLK_L_USBD
CLK_L_ISP
CLK_L_3D
CLK_L_DISP2
CLK_L_DISP1
CLK_L_HOST1X
CLK_L_VCP
CLK_L_I2S1
CLK_L_CACHE2
CLK_H_MEM
CLK_H_AHBDMA
CLK_H_APBDMA
CLK_H_KBC
CLK_H_STAT_MON
CLK_H_PMC
CLK_H_FUSE
CLK_H_KFUSE
CLK_H_SBC1
CLK_H_SNOR
CLK_H_JTAG2TBC
CLK_H_SBC2
CLK_H_SBC3
CLK_H_I2C5
CLK_H_DSI
CLK_H_HSI
CLK_H_HDMI
CLK_H_CSI
CLK_H_I2C2
CLK_H_UARTC
CLK_H_MIPI_CAL
CLK_H_EMC
CLK_H_USB2
CLK_H_USB3
CLK_H_MPE
CLK_H_VDE
CLK_H_BSEA
CLK_H_BSEV
CLK_U_UARTD
CLK_U_UARTE
CLK_U_I2C3
CLK_U_SBC4
CLK_U_SDMMC3
CLK_U_PCIE
CLK_U_OWR
CLK_U_AFI
CLK_U_CSITE
CLK_U_PCIEXCLK
CLK_U_AVPUCQ
CLK_U_TRACECLKIN
CLK_U_SOC_THERM
CLK_U_DTV
CLK_U_NAND_SPEED
CLK_U_I2C_SLOW
CLK_U_DSIB
CLK_U_TSEC
CLK_U_IRAMA
CLK_U_IRAMB
CLK_U_IRAMC
CLK_U_EMUCIF
CLK_U_IRAMD
CLK_U_CRAM2
CLK_U_XUSB_HOST
CLK_U_MSENC
CLK_U_SUS_OUT
CLK_U_DEV2_OUT
CLK_U_DEV1_OUT
CLK_U_XUSB_DEV
CLK_V_CPUG
CLK_V_CPULP
CLK_V_3D2
CLK_V_MSELECT
CLK_V_I2S4
CLK_V_I2S5
CLK_V_I2C4
CLK_V_SBC5
CLK_V_SBC6
CLK_V_AHUB
CLK_V_APB2APE
CLK_V_HDA2CODEC_2X
CLK_V_ATOMICS
CLK_V_ACTMON
CLK_V_EXTPERIPH1
CLK_V_SATA
CLK_V_HDA
CLK_W_HDA2HDMICODEC
CLK_W_SATACOLD
CLK_W_CEC
CLK_W_XUSB_PADCTL
CLK_W_ENTROPY
CLK_W_DVFS
CLK_W_XUSB_SS
CLK_X_GPU
CLK_X_SOR1
CLK_X_SOR0
CLK_X_DPAUX
CLK_X_VIC
CLK_X_UART_FST_MIPI_CAL
CLK_X_MIPIBIF
CLK_X_I2C6
CLK_X_ETR
CLK_X_SPARE
CLK_Y_APE
CLK_Y_DPAUX1
CLK_Y_QSPI
CLK_Y_SOR_SAFE

Definition at line 12 of file clock.h.

anonymous enum

anonymous enum

Enumerator
PLLP
PLLC2
PLLC
PLLC_OUT1
PLLM
CLK_M
CLK_S
PLLE
PLLA
PLLD
PLLD2
PLLC4_OUT0
PLLC4_OUT1
PLLC4_OUT2
PLLC4_OUT3
PLLC4_OUT0_L
PLLC4_OUT1_L
PLLC4_OUT2_L
PLLD_OUT0
PLLP_OUT3
PLLC2_OUT0
UNUSED0
UNUSED1
UNUSED2
UNUSED3
UNUSED4
UNUSED5
UNUSED6
UNUSED7

Definition at line 150 of file clock.h.

anonymous enum

anonymous enum

Enumerator
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE
CLK_SRC_DEVICE

Definition at line 203 of file clock.h.

Function Documentation

_clock_set_div()

static void _clock_set_div ( u32 *  reg, const char *  name, u32  div, u32  div_mask, u32  src  )

inlinestatic

Definition at line 298 of file clock.h.

References BIOS_ERR, CLK_DIVISOR_MASK, CLK_SOURCE_MASK, CLK_SOURCE_SHIFT, clrsetbits32, hlt(), name, and printk.

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clock_clr_reset_regs()

void clock_clr_reset_regs

(

u32

bits[DEV_CONFIG_BLOCKS]

)

Definition at line 707 of file clock.c.

References clock_write_regs(), and rst_dev_clr_arr.

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clock_configure_plld()

u32 clock_configure_plld

(

u32

frequency

)

plld (fo) = vco >> p, where 500MHz < vco < 1000MHz = (cf * n) >> p, where 1MHz < cf < 6MHz = ((ref / m) * n) >> p

Iterate the possible values of p (3 bits, 2^7) to find out a minimum safe vco, then find best (m, n). since m has only 5 bits, we can iterate all possible values. Note Tegra1xx supports 11 bits for n, but our pll_fields has only 10 bits for n.

Note values undershoot or overshoot target output frequency may not work if the values are not in "safe" range by panel specification.

Definition at line 385 of file clock.c.

References BIOS_DEBUG, BIOS_ERR, BIOS_WARNING, CLK_RST_REG, clock_get_osc_bits(), clock_get_pll_input_khz(), init_pll(), m, pll_fields::m, mhz, pll_fields::n, osc_table, pll_fields::p, PLLD_INDEX, PLLD_MISC1_SETUP, PLLD_MISC_EN_SDM, PLLD_MISC_SDM_DIN, printk, and write32().

Referenced by dp_display_startup(), dsi_display_startup(), enable_plld(), and tegra_output_dsi_setup_clock().

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clock_cpu0_config()

void clock_cpu0_config

(

void

)

clock_disable_regs()

void clock_disable_regs

(

u32

bits[DEV_CONFIG_BLOCKS]

)

Definition at line 697 of file clock.c.

References clk_enb_clr_arr, and clock_write_regs().

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clock_early_uart()

void clock_early_uart

(

void

)

Definition at line 386 of file clock.c.

References CLK_DIVIDER, CLK_L_UARTA, CLK_M, clk_rst_ctlr::clk_out_enb_l, clk_rst, CLK_SOURCE_SHIFT, clk_rst_ctlr::clk_src_uarta, CLK_UART_DIV_OVERRIDE, clrbits32, console_uart_clk_rst_reg(), console_uart_clk_src_dev_id(), console_uart_clock_enable_clear_reset(), console_uart_get_id(), clk_rst_ctlr::rst_dev_l, setbits32, TEGRA_CLK_M_KHZ, TEGRA_PLLP_KHZ, UART_ID_NONE, udelay(), and write32().

Referenced by tegra124_main(), and tegra210_main().

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clock_enable_audio()

void clock_enable_audio

(

void

)

Definition at line 772 of file clock.c.

References CLK_L_I2S1, CLK_L_I2S2, CLK_L_I2S3, CLK_L_SPDIF, CLK_V_AHUB, CLK_V_APB2APE, CLK_V_EXTPERIPH1, CLK_V_I2S4, CLK_V_I2S5, and clock_enable_clear_reset().

Referenced by setup_audio().

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clock_enable_clear_reset()

void clock_enable_clear_reset	(	u32	l,
		u32	h,
		u32	u,
		u32	v,
		u32	w,
		u32	x,
		u32	y
	)

Definition at line 712 of file clock.c.

References clock_clr_reset, clock_enable(), IO_STABILIZATION_DELAY, pll_fields::u, udelay(), x, and y.

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clock_enable_regs()

void clock_enable_regs

(

u32

bits[DEV_CONFIG_BLOCKS]

)

Definition at line 692 of file clock.c.

References clk_enb_set_arr, and clock_write_regs().

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clock_external_output()

void clock_external_output

(

int

clk_id

)

Definition at line 396 of file clock.c.

References BIOS_CRIT, tegra_pmc_regs::clk_out_cntrl, pmc, printk, and setbits32.

Referenced by mainboard_init().

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clock_get_osc_khz()

int clock_get_osc_khz

(

void

)

Definition at line 155 of file clock.c.

References clock_get_osc_bits(), and osc_table.

Referenced by arm64_arch_timer_init(), and clock_init_arm_generic_timer().

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clock_get_pll_input_khz()

int clock_get_pll_input_khz

(

void

)

Definition at line 160 of file clock.c.

References clk_rst, CLK_RST_REG, clk_rst_ctlr::osc_ctrl, OSC_FREQ_MASK, OSC_FREQ_SHIFT, OSC_PREDIV_MASK, OSC_PREDIV_SHIFT, osc_table, and read32().

Referenced by clock_configure_plld(), clock_display(), init_utmip_pll(), sdram_init(), and usb_setup_utmip().

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clock_grp_enable_clear_reset()

void clock_grp_enable_clear_reset	(	u32	val,
		u32 *	clk_enb_set_reg,
		u32 *	rst_dev_clr_reg
	)

Definition at line 634 of file clock.c.

References IO_STABILIZATION_DELAY, udelay(), val, and write32().

Referenced by soc_configure_funits().

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clock_halt_avp()

void clock_halt_avp

(

void

)

Definition at line 530 of file clock.c.

References flow, FLOW_EVENT_GIC_IRQ, FLOW_EVENT_JTAG, FLOW_EVENT_LIC_IRQ, FLOW_MODE_WAITEVENT, flow_ctlr::halt_cop_events, and write32().

Referenced by platform_prog_run(), and run_next_stage().

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clock_init()

void clock_init

(

void

)

Definition at line 539 of file clock.c.

clock_init_arm_generic_timer()

void clock_init_arm_generic_timer

(

void

)

Definition at line 168 of file clock.c.

References clock_get_osc_khz(), sysctr_regs::cntcr, sysctr_regs::cntfid0, read32(), set_cntfrq(), sysctr, SYSCTR_CNTCR_EN, SYSCTR_CNTCR_HDBG, TEGRA_CLK_M_KHZ, and write32().

Referenced by mainboard_init(), and ramstage_entry().

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clock_reset_h()

void clock_reset_h

(

u32

h

)

Definition at line 627 of file clock.c.

References clk_rst, CLK_RST_REG, clock_reset_dev(), clk_rst_ctlr::rst_dev_h_clr, clk_rst_ctlr::rst_dev_h_set, udelay(), and write32().

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clock_reset_l()

void clock_reset_l

(

u32

l

)

Definition at line 620 of file clock.c.

References clk_rst, CLK_RST_REG, clock_reset_dev(), clk_rst_ctlr::rst_dev_l_clr, clk_rst_ctlr::rst_dev_l_set, udelay(), and write32().

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clock_reset_u()

void clock_reset_u

(

u32

u

)

Definition at line 634 of file clock.c.

References clk_rst, CLK_RST_REG, clock_reset_dev(), clk_rst_ctlr::rst_dev_u_clr, clk_rst_ctlr::rst_dev_u_set, udelay(), and write32().

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clock_reset_v()

void clock_reset_v

(

u32

v

)

Definition at line 641 of file clock.c.

References clk_rst, CLK_RST_REG, clock_reset_dev(), clk_rst_ctlr::rst_dev_v_clr, clk_rst_ctlr::rst_dev_v_set, udelay(), and write32().

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clock_reset_w()

void clock_reset_w

(

u32

w

)

Definition at line 648 of file clock.c.

References clk_rst, CLK_RST_REG, clock_reset_dev(), clk_rst_ctlr::rst_dev_w_clr, clk_rst_ctlr::rst_dev_w_set, udelay(), and write32().

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clock_reset_x()

void clock_reset_x

(

u32

x

)

Definition at line 655 of file clock.c.

References clk_rst, CLK_RST_REG, clock_reset_dev(), clk_rst_ctlr::rst_dev_x_clr, clk_rst_ctlr::rst_dev_x_set, udelay(), and write32().

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clock_reset_y()

void clock_reset_y

(

u32

y

)

Definition at line 765 of file clock.c.

References CLK_RST_REG, and clock_reset_dev().

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clock_sdram()

void clock_sdram	(	u32	m,
		u32	n,
		u32	p,
		u32	setup,
		u32	kvco,
		u32	kcp,
		u32	stable_time,
		u32	emc_source,
		u32	same_freq
	)

Definition at line 512 of file clock.c.

References base, CLK_H_EMC, CLK_H_MEM, CLK_RST_REG, CLK_SOURCE_EMC_MC_EMC_SAME_FREQ, clock_enable_clear_reset(), IO_STABILIZATION_DELAY, pll_fields::kcp, pll_fields::kvco, m, pll_fields::n, pll_fields::p, PLL_BASE_BYPASS, PLL_BASE_DIVM_SHIFT, PLL_BASE_DIVN_SHIFT, PLL_BASE_DIVP_SHIFT, PLL_BASE_ENABLE, PLL_BASE_LOCK, PLLCMX_BASE_DIVM_MASK, PLLCMX_BASE_DIVN_MASK, PLLM_BASE_DIVP_MASK, PLLM_EN_LCKDET, PLLM_MISC1_SETUP_SHIFT, PLLM_MISC2_KCP_SHIFT, PLLM_MISC2_KVCO_SHIFT, read32(), setbits32, udelay(), and write32().

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clock_set_reset_regs()

void clock_set_reset_regs

(

u32

bits[DEV_CONFIG_BLOCKS]

)

Definition at line 702 of file clock.c.

References clock_write_regs(), and rst_dev_set_arr.

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sor_clock_start()

void sor_clock_start

(

void

)

Definition at line 195 of file clock.c.

References clk_rst, CLK_RST_REG, clk_rst_ctlr::clk_src_sor, setbits32, and SOR0_CLK_SEL0.

Referenced by tegra_sor_enable_edp_clock().

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sor_clock_stop()

void sor_clock_stop

(

void

)

Definition at line 185 of file clock.c.

References clk_rst, CLK_RST_REG, clk_rst_ctlr::clk_src_sor, clrbits32, SOR0_CLK_SEL0, and SOR0_CLK_SEL1.