14 #include <soc/symbols.h>
17 #define SPM_SYSTEM_BASE_OFFSET 0x40000000
30 .reg_mp0_cputop_idle_mask = 0,
31 .reg_mp1_cputop_idle_mask = 0,
32 .reg_mcusys_idle_mask = 0,
33 .reg_md_apsrc_1_sel = 0,
34 .reg_md_apsrc_0_sel = 0,
35 .reg_conn_apsrc_sel = 0,
38 .reg_ccif_event_infra_req_mask_b = 0xFFFF,
39 .reg_ccif_event_apsrc_req_mask_b = 0xFFFF,
42 .reg_spm_apsrc_req = 0,
43 .reg_spm_f26m_req = 0,
44 .reg_spm_infra_req = 0,
45 .reg_spm_vrf18_req = 0,
46 .reg_spm_ddren_req = 0,
47 .reg_spm_dvfs_req = 0,
48 .reg_spm_sw_mailbox_req = 0,
49 .reg_spm_sspm_mailbox_req = 0,
50 .reg_spm_adsp_mailbox_req = 0,
51 .reg_spm_scp_mailbox_req = 0,
54 .reg_md_0_srcclkena_mask_b = 1,
55 .reg_md_0_infra_req_mask_b = 1,
56 .reg_md_0_apsrc_req_mask_b = 1,
57 .reg_md_0_vrf18_req_mask_b = 1,
58 .reg_md_0_ddren_req_mask_b = 1,
59 .reg_md_1_srcclkena_mask_b = 0,
60 .reg_md_1_infra_req_mask_b = 0,
61 .reg_md_1_apsrc_req_mask_b = 0,
62 .reg_md_1_vrf18_req_mask_b = 0,
63 .reg_md_1_ddren_req_mask_b = 0,
64 .reg_conn_srcclkena_mask_b = 1,
65 .reg_conn_srcclkenb_mask_b = 0,
66 .reg_conn_infra_req_mask_b = 1,
67 .reg_conn_apsrc_req_mask_b = 1,
68 .reg_conn_vrf18_req_mask_b = 1,
69 .reg_conn_ddren_req_mask_b = 1,
70 .reg_conn_vfe28_mask_b = 0,
71 .reg_srcclkeni_srcclkena_mask_b = 1,
72 .reg_srcclkeni_infra_req_mask_b = 1,
73 .reg_infrasys_apsrc_req_mask_b = 0,
74 .reg_infrasys_ddren_req_mask_b = 1,
75 .reg_sspm_srcclkena_mask_b = 1,
76 .reg_sspm_infra_req_mask_b = 1,
77 .reg_sspm_apsrc_req_mask_b = 1,
78 .reg_sspm_vrf18_req_mask_b = 1,
79 .reg_sspm_ddren_req_mask_b = 1,
82 .reg_scp_srcclkena_mask_b = 1,
83 .reg_scp_infra_req_mask_b = 1,
84 .reg_scp_apsrc_req_mask_b = 1,
85 .reg_scp_vrf18_req_mask_b = 1,
86 .reg_scp_ddren_req_mask_b = 1,
87 .reg_audio_dsp_srcclkena_mask_b = 1,
88 .reg_audio_dsp_infra_req_mask_b = 1,
89 .reg_audio_dsp_apsrc_req_mask_b = 1,
90 .reg_audio_dsp_vrf18_req_mask_b = 1,
91 .reg_audio_dsp_ddren_req_mask_b = 1,
92 .reg_ufs_srcclkena_mask_b = 1,
93 .reg_ufs_infra_req_mask_b = 1,
94 .reg_ufs_apsrc_req_mask_b = 1,
95 .reg_ufs_vrf18_req_mask_b = 1,
96 .reg_ufs_ddren_req_mask_b = 1,
97 .reg_disp0_apsrc_req_mask_b = 1,
98 .reg_disp0_ddren_req_mask_b = 1,
99 .reg_disp1_apsrc_req_mask_b = 1,
100 .reg_disp1_ddren_req_mask_b = 1,
101 .reg_gce_infra_req_mask_b = 1,
102 .reg_gce_apsrc_req_mask_b = 1,
103 .reg_gce_vrf18_req_mask_b = 1,
104 .reg_gce_ddren_req_mask_b = 1,
105 .reg_apu_srcclkena_mask_b = 0,
106 .reg_apu_infra_req_mask_b = 0,
107 .reg_apu_apsrc_req_mask_b = 0,
108 .reg_apu_vrf18_req_mask_b = 0,
109 .reg_apu_ddren_req_mask_b = 0,
110 .reg_cg_check_srcclkena_mask_b = 0,
111 .reg_cg_check_apsrc_req_mask_b = 0,
112 .reg_cg_check_vrf18_req_mask_b = 0,
113 .reg_cg_check_ddren_req_mask_b = 0,
116 .reg_dvfsrc_event_trigger_mask_b = 1,
117 .reg_sw2spm_wakeup_mask_b = 0,
118 .reg_adsp2spm_wakeup_mask_b = 0,
119 .reg_sspm2spm_wakeup_mask_b = 0,
120 .reg_scp2spm_wakeup_mask_b = 0,
121 .reg_csyspwrup_ack_mask = 1,
122 .reg_spm_reserved_srcclkena_mask_b = 0,
123 .reg_spm_reserved_infra_req_mask_b = 0,
124 .reg_spm_reserved_apsrc_req_mask_b = 0,
125 .reg_spm_reserved_vrf18_req_mask_b = 0,
126 .reg_spm_reserved_ddren_req_mask_b = 0,
127 .reg_mcupm_srcclkena_mask_b = 1,
128 .reg_mcupm_infra_req_mask_b = 1,
129 .reg_mcupm_apsrc_req_mask_b = 1,
130 .reg_mcupm_vrf18_req_mask_b = 1,
131 .reg_mcupm_ddren_req_mask_b = 1,
132 .reg_msdc0_srcclkena_mask_b = 1,
133 .reg_msdc0_infra_req_mask_b = 1,
134 .reg_msdc0_apsrc_req_mask_b = 1,
135 .reg_msdc0_vrf18_req_mask_b = 1,
136 .reg_msdc0_ddren_req_mask_b = 1,
137 .reg_msdc1_srcclkena_mask_b = 1,
138 .reg_msdc1_infra_req_mask_b = 1,
139 .reg_msdc1_apsrc_req_mask_b = 1,
140 .reg_msdc1_vrf18_req_mask_b = 1,
141 .reg_msdc1_ddren_req_mask_b = 1,
144 .reg_ccif_event_srcclkena_mask_b = 0x3FF,
145 .reg_bak_psri_srcclkena_mask_b = 0,
146 .reg_bak_psri_infra_req_mask_b = 0,
147 .reg_bak_psri_apsrc_req_mask_b = 0,
148 .reg_bak_psri_vrf18_req_mask_b = 0,
149 .reg_bak_psri_ddren_req_mask_b = 0,
150 .reg_dramc_md32_infra_req_mask_b = 1,
151 .reg_dramc_md32_vrf18_req_mask_b = 0,
152 .reg_conn_srcclkenb2pwrap_mask_b = 0,
153 .reg_dramc_md32_apsrc_req_mask_b = 0,
156 .reg_mcusys_merge_apsrc_req_mask_b = 0x14,
157 .reg_mcusys_merge_ddren_req_mask_b = 0x14,
158 .reg_afe_srcclkena_mask_b = 0,
159 .reg_afe_infra_req_mask_b = 0,
160 .reg_afe_apsrc_req_mask_b = 0,
161 .reg_afe_vrf18_req_mask_b = 0,
162 .reg_afe_ddren_req_mask_b = 0,
163 .reg_msdc2_srcclkena_mask_b = 0,
164 .reg_msdc2_infra_req_mask_b = 0,
165 .reg_msdc2_apsrc_req_mask_b = 0,
166 .reg_msdc2_vrf18_req_mask_b = 0,
167 .reg_msdc2_ddren_req_mask_b = 0,
170 .reg_wakeup_event_mask = 0xEFFFFFFF,
173 .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
176 .reg_pcie_srcclkena_mask_b = 0,
177 .reg_pcie_infra_req_mask_b = 0,
178 .reg_pcie_apsrc_req_mask_b = 0,
179 .reg_pcie_vrf18_req_mask_b = 0,
180 .reg_pcie_ddren_req_mask_b = 0,
181 .reg_dpmaif_srcclkena_mask_b = 1,
182 .reg_dpmaif_infra_req_mask_b = 1,
183 .reg_dpmaif_apsrc_req_mask_b = 1,
184 .reg_dpmaif_vrf18_req_mask_b = 1,
185 .reg_dpmaif_ddren_req_mask_b = 1,
375 SPM_ACK_CHK_3_CON_EN_0, 1,
376 SPM_ACK_CHK_3_CON_EN_1, 1);
379 SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 1,
380 SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 1,
382 SPM_ACK_CHK_3_CON_EN_0, 0,
383 SPM_ACK_CHK_3_CON_EN_1, 0);
456 INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 1,
457 INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 1);
479 bool first_load_fw =
true;
483 first_load_fw =
false;
485 if (!first_load_fw) {
521 dmem_words = total_words - pmem_words;
526 __func__, (
long)ptr, pmem_words, dmem_words);
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
#define assert(statement)
void spm_parse_firmware(struct mtk_mcu *mcu)
#define printk(level,...)
#define setbits32(addr, set)
#define SET32_BITFIELDS(addr,...)
#define clrsetbits32(addr, clear, set)
#define REGION_SIZE(name)
static void stopwatch_init(struct stopwatch *sw)
static long stopwatch_duration_msecs(struct stopwatch *sw)
#define BIOS_INFO
BIOS_INFO - Expected events.
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
int mtk_init_mcu(struct mtk_mcu *mcu)
static struct mtk_spm_regs *const mtk_spm
#define SPM_WAKEUP_EVENT_MASK_DEF
#define SPM_REGWR_CFG_KEY
#define POWER_ON_VAL1_DEF
#define REG_DDREN_DBC_EN_LSB
#define SPM_FLAG_DISABLE_VCORE_DVS
#define REG_MD32_APB_INTERNAL_EN_LSB
#define SPM_ACK_CHK_3_SEL_HW_S1
#define ARMPLL_CLK_SEL_DEF
#define RG_PCM_WDT_WAKE_LSB
#define MD32PCM_CFGREG_SW_RSTN
#define MD32PCM_DMA0_START_VAL
#define SPM_RESOURCE_ACK_CON0_DEF
#define MD32PCM_DMA0_START
#define MD32PCM_DMA0_RLCT
#define SPM_BUS_PROTECT2_MASK_B_DEF
#define MD32PCM_DMA0_WPPT
#define MD32PCM_DMA0_CON_VAL
#define SPM_ACK_CHK_3_HW_S1_CNT
#define SPM_FLAG_DISABLE_VCORE_DFS
#define SPM_RESOURCE_ACK_CON2_DEF
#define MD32PCM_CFGREG_SW_RSTN_RUN
#define SPM_RESOURCE_ACK_CON1_DEF
#define SPM_RESOURCE_ACK_CON3_DEF
#define MD32PCM_DMA0_WPTO
#define REG_SPM_EVENT_COUNTER_CLR_LSB
#define SPM_WAKEUP_EVENT_MASK_BIT0
#define SPM_SYSCLK_SETTLE
#define SPM_BUS_PROTECT_MASK_B_DEF
#define RG_PCM_TIMER_EN_LSB
#define RG_AHBMIF_APBEN_LSB
#define SPM_DVS_DFS_LEVEL_DEF
#define SPM_FLAG_RUN_COMMON_SCENARIO
#define MD32PCM_DMA0_COUNT
#define SPM_DVFS_LEVEL_DEF
static void spm_hw_s1_state_monitor(int en)
static void spm_code_swapping(void)
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
static void spm_extern_initialize(void)
static void reset_spm(struct mtk_mcu *mcu)
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
static void spm_init_pcm_register(void)
static void spm_reset_and_init_pcm(void)
static void spm_set_sysclk_settle(void)
static void spm_register_init(void)
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
static struct mtk_mcu spm
#define SPM_SYSTEM_BASE_OFFSET
static const struct pwr_ctrl spm_init_ctrl
#define SYS_TIMER_START_EN_LSB
#define SPM_DVFSRC_ENABLE_LSB
#define SPM_DVFS_FORCE_ENABLE_LSB
#define MD32PCM_CFGREG_SW_RSTN_RESET
#define REG_SYSCLK1_SRC_MD2_SRCCLKENA
#define SPM_ACK_CHK_3_CON_CLR_ALL
const char * firmware_name
uint32_t spm_bus_protect_mask_b
uint32_t spm_resource_ack_con2
uint32_t spm_resource_ack_con1
uint32_t spm_bus_protect2_mask_b
uint32_t spm_dvs_dfs_level
u32 spm_wakeup_event_ext_mask
uint32_t spm_ack_chk_timer_3
uint32_t spm_resource_ack_con0
u32 spm_wakeup_event_mask
uint32_t spm_ack_chk_sel_3
uint32_t spm_resource_ack_con3
uint32_t spm_ack_chk_con_3
uint8_t reg_md_1_infra_req_mask_b
uint8_t reg_sspm_apsrc_req_mask_b
uint8_t reg_dpmaif_srcclkena_mask_b
uint8_t reg_conn_vfe28_mask_b
uint8_t reg_bak_psri_apsrc_req_mask_b
uint8_t reg_gce_ddren_req_mask_b
uint8_t reg_msdc1_infra_req_mask_b
uint8_t reg_apu_vrf18_req_mask_b
uint8_t reg_apu_infra_req_mask_b
uint8_t reg_spm_reserved_apsrc_req_mask_b
uint8_t reg_scp_ddren_req_mask_b
uint8_t reg_ufs_infra_req_mask_b
uint8_t reg_md_1_ddren_req_mask_b
uint8_t reg_disp0_ddren_req_mask_b
uint8_t reg_msdc0_vrf18_req_mask_b
uint8_t reg_ufs_srcclkena_mask_b
uint8_t reg_conn_ddren_req_mask_b
uint8_t reg_pcie_ddren_req_mask_b
uint8_t reg_audio_dsp_ddren_req_mask_b
uint8_t reg_msdc2_srcclkena_mask_b
uint8_t reg_gce_vrf18_req_mask_b
uint8_t reg_disp0_apsrc_req_mask_b
uint8_t reg_cg_check_vrf18_req_mask_b
uint8_t reg_disp1_apsrc_req_mask_b
uint8_t reg_ufs_apsrc_req_mask_b
uint8_t reg_dramc_md32_vrf18_req_mask_b
uint8_t reg_sspm2spm_wakeup_mask_b
uint8_t reg_spm_reserved_infra_req_mask_b
uint8_t reg_md_0_ddren_req_mask_b
uint8_t reg_srcclkeni_srcclkena_mask_b
uint8_t reg_infrasys_ddren_req_mask_b
uint8_t reg_scp_infra_req_mask_b
uint8_t reg_msdc0_srcclkena_mask_b
uint32_t pcm_flags_cust_set
uint8_t reg_msdc2_apsrc_req_mask_b
uint8_t reg_sspm_infra_req_mask_b
uint8_t reg_afe_srcclkena_mask_b
uint8_t reg_pcie_vrf18_req_mask_b
uint8_t reg_audio_dsp_apsrc_req_mask_b
uint8_t reg_spm_vrf18_req
uint8_t reg_spm_reserved_srcclkena_mask_b
uint8_t reg_msdc2_vrf18_req_mask_b
uint8_t reg_bak_psri_ddren_req_mask_b
uint8_t reg_gce_infra_req_mask_b
uint8_t reg_msdc0_infra_req_mask_b
uint8_t reg_conn_srcclkenb_mask_b
uint8_t reg_md_0_infra_req_mask_b
uint8_t reg_conn_srcclkenb2pwrap_mask_b
uint32_t reg_wakeup_event_mask
uint8_t reg_afe_infra_req_mask_b
uint8_t reg_disp1_ddren_req_mask_b
uint8_t reg_md_0_apsrc_req_mask_b
uint8_t reg_dpmaif_apsrc_req_mask_b
uint8_t reg_scp_vrf18_req_mask_b
uint8_t reg_dramc_md32_infra_req_mask_b
uint8_t reg_sw2spm_wakeup_mask_b
uint32_t reg_ccif_event_apsrc_req_mask_b
uint8_t reg_apu_srcclkena_mask_b
uint8_t reg_md_apsrc_1_sel
uint8_t reg_md_1_vrf18_req_mask_b
uint8_t reg_msdc2_infra_req_mask_b
uint8_t reg_spm_reserved_ddren_req_mask_b
uint8_t reg_mcupm_vrf18_req_mask_b
uint32_t reg_ccif_event_infra_req_mask_b
uint8_t reg_bak_psri_vrf18_req_mask_b
uint8_t reg_apu_apsrc_req_mask_b
uint8_t reg_spm_ddren_req
uint8_t reg_scp2spm_wakeup_mask_b
uint32_t pcm_flags_cust_clr
uint8_t reg_conn_apsrc_sel
uint8_t reg_spm_adsp_mailbox_req
uint8_t reg_mcupm_apsrc_req_mask_b
uint8_t reg_audio_dsp_infra_req_mask_b
uint8_t reg_dpmaif_infra_req_mask_b
uint8_t reg_afe_ddren_req_mask_b
uint8_t reg_infrasys_apsrc_req_mask_b
uint8_t reg_md_0_srcclkena_mask_b
uint8_t reg_mp1_cputop_idle_mask
uint8_t reg_conn_srcclkena_mask_b
uint8_t reg_audio_dsp_vrf18_req_mask_b
uint8_t reg_md_1_apsrc_req_mask_b
uint8_t reg_bak_psri_srcclkena_mask_b
uint8_t reg_msdc2_ddren_req_mask_b
uint8_t reg_msdc1_vrf18_req_mask_b
uint8_t reg_cg_check_srcclkena_mask_b
uint8_t reg_msdc1_apsrc_req_mask_b
uint8_t reg_md_apsrc_0_sel
uint8_t reg_gce_apsrc_req_mask_b
uint8_t reg_mcusys_idle_mask
uint8_t reg_spm_sspm_mailbox_req
uint8_t reg_mcupm_infra_req_mask_b
uint8_t reg_sspm_ddren_req_mask_b
uint8_t reg_dpmaif_vrf18_req_mask_b
uint32_t reg_mcusys_merge_ddren_req_mask_b
uint8_t reg_spm_reserved_vrf18_req_mask_b
uint8_t reg_scp_apsrc_req_mask_b
uint8_t reg_pcie_apsrc_req_mask_b
uint8_t reg_conn_apsrc_req_mask_b
uint8_t reg_cg_check_apsrc_req_mask_b
uint8_t reg_mcupm_srcclkena_mask_b
uint8_t reg_sspm_vrf18_req_mask_b
uint8_t reg_ufs_vrf18_req_mask_b
uint8_t reg_cg_check_ddren_req_mask_b
uint8_t reg_conn_infra_req_mask_b
uint32_t pcm_flags1_cust_set
uint8_t reg_msdc0_ddren_req_mask_b
uint8_t reg_dramc_md32_apsrc_req_mask_b
uint32_t reg_mcusys_merge_apsrc_req_mask_b
uint32_t pcm_flags1_cust_clr
uint8_t reg_afe_apsrc_req_mask_b
uint8_t reg_pcie_srcclkena_mask_b
uint8_t reg_msdc1_srcclkena_mask_b
uint8_t reg_conn_vrf18_req_mask_b
uint8_t reg_csyspwrup_ack_mask
uint8_t reg_pcie_infra_req_mask_b
uint8_t reg_srcclkeni_infra_req_mask_b
uint8_t reg_afe_vrf18_req_mask_b
uint8_t reg_sspm_srcclkena_mask_b
uint32_t reg_ext_wakeup_event_mask
uint8_t reg_msdc0_apsrc_req_mask_b
uint8_t reg_msdc1_ddren_req_mask_b
uint8_t reg_scp_srcclkena_mask_b
uint8_t reg_bak_psri_infra_req_mask_b
uint8_t reg_md_1_srcclkena_mask_b
uint8_t reg_spm_sw_mailbox_req
uint8_t reg_spm_infra_req
uint8_t reg_spm_apsrc_req
uint8_t reg_dvfsrc_event_trigger_mask_b
uint8_t reg_adsp2spm_wakeup_mask_b
uint8_t reg_md_0_vrf18_req_mask_b
uint8_t reg_apu_ddren_req_mask_b
uint8_t reg_audio_dsp_srcclkena_mask_b
uint32_t reg_ccif_event_srcclkena_mask_b
uint8_t reg_dpmaif_ddren_req_mask_b
uint8_t reg_spm_scp_mailbox_req
uint8_t reg_mp0_cputop_idle_mask
uint8_t reg_mcupm_ddren_req_mask_b
uint8_t reg_ufs_ddren_req_mask_b