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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/rcba.h>
#include <soc/romstage.h>
#include <soc/intel/broadwell/pch/chip.h>
Go to the source code of this file.
Functions | |
static void | pch_route_interrupts (void) |
static void | pch_enable_lpc (void) |
void | pch_early_init (void) |
Definition at line 67 of file early_pch.c.
References _PCH_DEV, enable_smbus(), pch_enable_lpc(), pch_route_interrupts(), pci_and_config32(), and pci_or_config32().
Referenced by mainboard_romstage_entry().
Definition at line 51 of file early_pch.c.
References device::chip_info, config, LPC_GEN1_DEC, LPC_GEN2_DEC, LPC_GEN3_DEC, LPC_GEN4_DEC, PCH_DEV_LPC, pci_write_config32(), and pcidev_on_root().
Referenced by bootblock_early_southbridge_init(), bootblock_soc_early_init(), pch_early_init(), and pch_early_iorange_init().
Definition at line 16 of file early_pch.c.
References D20IP, D20IP_XHCI, D20IR, D21IR, D22IP, D22IP_MEI1IP, D22IR, D23IR, D26IP, D26IP_E2P, D27IP, D27IP_ZIP, D27IR, D28IP, D28IP_P1IP, D28IP_P3IP, D28IP_P4IP, D28IR, D29IP, D29IP_E1P, D29IR, D31IP, D31IP_SIP, D31IP_SIP2, D31IP_SMIP, D31IP_TTIP, D31IR, DIR_ROUTE, INTA, INTB, INTC, NOINT, PIRQA, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH, and RCBA32.
Referenced by pch_early_init().