19 #include <soc/bootblock.h>
21 #include <soc/iomap.h>
23 #include <soc/pci_devs.h>
24 #include <soc/pcr_ids.h>
27 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
28 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1080
30 #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100
33 #define PCR_PSFX_TO_SHDW_BAR0 0
34 #define PCR_PSFX_TO_SHDW_BAR1 0x4
35 #define PCR_PSFX_TO_SHDW_BAR2 0x8
36 #define PCR_PSFX_TO_SHDW_BAR3 0xC
37 #define PCR_PSFX_TO_SHDW_BAR4 0x10
38 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
39 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C
85 if (pmc_reg_value != 0xffffffff) {
104 if (
CONFIG(DRIVERS_UART_8250IO))
void p2sb_enable_bar(void)
void p2sb_configure_hpet(void)
void pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata)
void pcr_rmw32(uint8_t pid, uint16_t offset, uint32_t anddata, uint32_t ordata)
uint32_t pcr_read32(uint8_t pid, uint16_t offset)
void fast_spi_early_init(uintptr_t spi_base_address)
void gspi_early_bar_init(void)
#define setbits32(addr, set)
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
static __always_inline void pci_and_config16(const struct device *dev, u16 reg, u16 andmask)
static __always_inline void pci_or_config16(const struct device *dev, u16 reg, u16 ormask)
#define PCH_PWRM_BASE_ADDRESS
#define ACPI_BASE_ADDRESS
#define LPC_IOE_SUPERIO_2E_2F
#define LPC_IOE_KBC_60_64
uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
void lpc_io_setup_comm_a_b(void)
#define PCI_COMMAND_MASTER
#define PCI_COMMAND_MEMORY
#define PCR_PSFX_T0_SHDW_PCIEN
void bootblock_pch_init(void)
void bootblock_pch_early_init(void)
static void soc_config_pwrmbase(void)
#define PCR_PSF3_TO_SHDW_PMC_REG_BASE
#define PCR_PSFX_TO_SHDW_BAR4
void pch_early_iorange_init(void)
static void soc_config_acpibase(void)
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN
static void pch_enable_lpc(void)
void enable_rtc_upper_bank(void)