acpi.c

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/* SPDX-License-Identifier: GPL-2.0-only */
 
#include <acpi/acpi.h>
#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/acpi.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/soc_chip.h>
#include <soc/systemagent.h>
 
/*
 * List of supported C-states in this processor.
 */
enum {
        C_STATE_C0,             /* 0 */
        C_STATE_C1,             /* 1 */
        C_STATE_C1E,            /* 2 */
        C_STATE_C6_SHORT_LAT,   /* 3 */
        C_STATE_C6_LONG_LAT,    /* 4 */
        C_STATE_C7_SHORT_LAT,   /* 5 */
        C_STATE_C7_LONG_LAT,    /* 6 */
        C_STATE_C7S_SHORT_LAT,  /* 7 */
        C_STATE_C7S_LONG_LAT,   /* 8 */
        C_STATE_C8,             /* 9 */
        C_STATE_C9,             /* 10 */
        C_STATE_C10,            /* 11 */
        NUM_C_STATES
};
 
static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
        [C_STATE_C0] = {},
        [C_STATE_C1] = {
                .latency = 0,
                .power = C1_POWER,
                .resource = MWAIT_RES(0, 0),
        },
        [C_STATE_C1E] = {
                .latency = 0,
                .power = C1_POWER,
                .resource = MWAIT_RES(0, 1),
        },
        [C_STATE_C6_SHORT_LAT] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C6_POWER,
                .resource = MWAIT_RES(2, 0),
        },
        [C_STATE_C6_LONG_LAT] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C6_POWER,
                .resource = MWAIT_RES(2, 1),
        },
        [C_STATE_C7_SHORT_LAT] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C7_POWER,
                .resource = MWAIT_RES(3, 0),
        },
        [C_STATE_C7_LONG_LAT] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C7_POWER,
                .resource = MWAIT_RES(3, 1),
        },
        [C_STATE_C7S_SHORT_LAT] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C7_POWER,
                .resource = MWAIT_RES(3, 2),
        },
        [C_STATE_C7S_LONG_LAT] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C7_POWER,
                .resource = MWAIT_RES(3, 3),
        },
        [C_STATE_C8] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C8_POWER,
                .resource = MWAIT_RES(4, 0),
        },
        [C_STATE_C9] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C9_POWER,
                .resource = MWAIT_RES(5, 0),
        },
        [C_STATE_C10] = {
                .latency = C_STATE_LATENCY_FROM_LAT_REG(0),
                .power = C10_POWER,
                .resource = MWAIT_RES(6, 0),
        },
};
 
static int cstate_set_non_s0ix[] = {
        C_STATE_C1E,
        C_STATE_C6_LONG_LAT,
        C_STATE_C7S_LONG_LAT
};
 
static int cstate_set_s0ix[] = {
        C_STATE_C1E,
        C_STATE_C7S_LONG_LAT,
        C_STATE_C10
};
 
const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
{
        static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
                                ARRAY_SIZE(cstate_set_non_s0ix))];
        int *set;
        int i;
 
        config_t *config = config_of_soc();
 
        int is_s0ix_enable = config->s0ix_enable;
 
        if (is_s0ix_enable) {
                *entries = ARRAY_SIZE(cstate_set_s0ix);
                set = cstate_set_s0ix;
        } else {
                *entries = ARRAY_SIZE(cstate_set_non_s0ix);
                set = cstate_set_non_s0ix;
        }
 
        for (i = 0; i < *entries; i++) {
                map[i] = cstate_map[set[i]];
                map[i].ctype = i + 1;
        }
        return map;
}
 
void soc_power_states_generation(int core_id, int cores_per_package)
{
        config_t *config = config_of_soc();
 
        if (config->eist_enable)
                /* Generate P-state tables */
                generate_p_state_entries(core_id, cores_per_package);
}
 
void soc_fill_fadt(acpi_fadt_t *fadt)
{
        const uint16_t pmbase = ACPI_BASE_ADDRESS;
 
        config_t *config = config_of_soc();
 
        fadt->pm_tmr_blk = pmbase + PM1_TMR;
        fadt->pm_tmr_len = 4;
        fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
        fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
        fadt->x_pm_tmr_blk.bit_offset = 0;
        fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
        fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
        fadt->x_pm_tmr_blk.addrh = 0x0;
 
        if (config->s0ix_enable)
                fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
}
uint32_t soc_read_sci_irq_select(void)
{
        return read32p(soc_read_pmc_base() + IRQ_REG);
}
 
void soc_fill_gnvs(struct global_nvs *gnvs)
{
        config_t *config = config_of_soc();
 
        /* Enable DPTF based on mainboard configuration */
        gnvs->dpte = config->dptf_enable;
 
        /* Set USB2/USB3 wake enable bitmaps. */
        gnvs->u2we = config->usb2_wake_enable_bitmap;
        gnvs->u3we = config->usb3_wake_enable_bitmap;
 
        /* Fill in Above 4GB MMIO resource */
        sa_fill_gnvs(gnvs);
}
 
int soc_madt_sci_irq_polarity(int sci)
{
        return MP_IRQ_POLARITY_HIGH;
}