coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/ioapic.h>
#include <console/console.h>
#include <console/debug.h>
#include <cpu/x86/mp.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <intelblocks/acpi.h>
#include <intelblocks/gpio.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/p2sb.h>
#include <soc/acpi.h>
#include <soc/chip_common.h>
#include <soc/cpu.h>
#include <soc/pch.h>
#include <soc/ramstage.h>
#include <soc/p2sb.h>
#include <soc/soc_util.h>
#include <soc/util.h>
#include <soc/pci_devs.h>
Go to the source code of this file.
Functions | |
void | platform_fsp_silicon_init_params_cb (FSPS_UPD *silupd) |
static void | chip_enable_dev (struct device *dev) |
static void | iio_write_mask (u16 bus, u16 dev, u8 func) |
static void | iio_dmi_en_masks (void) |
static void | iio_enable_masks (void) |
static void | set_pcu_locks (void) |
static void | set_imc_locks (void) |
static void | set_upi_locks (void) |
static void | chip_final (void *data) |
static void | chip_init (void *data) |
Variables | |
static struct device_operations | pci_domain_ops |
static struct device_operations | cpu_bus_ops |
struct pci_operations | soc_pci_ops |
struct chip_operations | soc_intel_xeon_sp_cpx_ops |
Definition at line 59 of file chip.c.
References attach_iio_stacks(), block_gpio_enable(), cpu_bus_ops, DEVICE_PATH_CPU_CLUSTER, DEVICE_PATH_DOMAIN, DEVICE_PATH_GPIO, device::ops, device::path, pci_domain_ops, and device_path::type.
Definition at line 159 of file chip.c.
References iio_enable_masks(), p2sb_hide(), P2SBC, PCH_DEV_P2SB, PCI_DEVFN, pci_or_config32(), pcidev_path_on_root(), SBILOCK, set_bios_init_completion(), set_imc_locks(), set_pcu_locks(), and set_upi_locks().
Definition at line 176 of file chip.c.
References BIOS_DEBUG, fsp_silicon_init(), override_hpet_ioapic_bdf(), p2sb_unhide(), pch_enable_ioapic(), pch_lock_dmictl(), and printk.
Definition at line 84 of file chip.c.
References device, DLL_PRT_ERR, DMI_BUS_INDEX, DMI_DEV, DMI_FUNC, DMI_UNCERRMSK, ECRC_ERR, FLOW_CNTR, IIO_XPUNCCERRMSK_REG, MLFRMD_TLP, PCI_DEV, pci_s_read_config32(), pci_s_write_config32(), POISON_TLP, RCV_BUF_OVRFLOW, RCVD_PCIE_CA_STS_MASK, RCVD_PCIE_UR_STS_MASK, SENT_PCIE_UNSUPP_MASK, and val.
Referenced by iio_enable_masks().
Definition at line 98 of file chip.c.
References BIOS_DEBUG, DEVICES_PER_IIO_STACK, get_iiostack_info(), iio_dmi_en_masks(), iio_write_mask(), iiostack_resource::no_of_stacks, printk, and iiostack_resource::res.
Referenced by chip_final().
Definition at line 72 of file chip.c.
References IIO_XPUNCCERRMSK_REG, PCI_DEV, pci_s_read_config32(), pci_s_write_config32(), RCVD_PCIE_CA_STS_MASK, RCVD_PCIE_UR_STS_MASK, RP_UNCERRMSK, SENT_PCIE_UNSUPP_MASK, SURPRISE_DWN_ERR_MSK, UNSUPPORTED_REQ_ERR_MSK, and val.
Referenced by iio_enable_masks().
Definition at line 145 of file chip.c.
References dev_find_device(), IMC_M2MEM_DEVID, IMC_M2MEM_TIMEOUT, pci_or_config32(), PCI_VID_INTEL, and TIMEOUT_LOCK.
Referenced by chip_final().
Definition at line 116 of file chip.c.
References DRAM_POWER_INFO_LOCK_UPR, get_socket_stack_busno(), OC_LOCK, P_STATE_LIMITS_LOCK, pci_or_config32(), PCU_CR0_P_STATE_LIMITS, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PCU_CR0_TURBO_ACTIVATION_RATIO, PCU_CR1_SAPMCTL, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PCU_CR2_DRAM_POWER_INFO_UPR, PCU_CR3_CONFIG_TDP_CONTROL, PCU_CR3_FLEX_RATIO, PCU_DEV_CR0, PCU_DEV_CR1, PCU_DEV_CR2, PCU_DEV_CR3, PCU_IIO_STACK, PKG_PWR_LIM_LOCK_UPR, PP_PWR_LIM_LOCK, SAPMCTL_LOCK_MASK, soc_get_num_cpus(), TDP_LOCK, and TURBO_ACTIVATION_RATIO_LOCK.
Referenced by chip_final().
Definition at line 152 of file chip.c.
References dev_find_device(), KTIMISCMODLCK_LOCK, pci_or_config32(), PCI_VID_INTEL, UPI_LL_CR_DEVID, and UPI_LL_CR_KTIMISCMODLCK.
Referenced by chip_final().
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Definition at line 24 of file chip.c.
Referenced by chip_enable_dev().
struct chip_operations soc_intel_xeon_sp_cpx_ops |
struct pci_operations soc_pci_ops |