10 #include <soc/symbols.h>
13 #define SPM_SYSTEM_BASE_OFFSET 0x40000000
25 .reg_mp0_cputop_idle_mask = 0,
27 .reg_mp1_cputop_idle_mask = 0,
29 .reg_mcusys_idle_mask = 0,
31 .reg_md_apsrc_1_sel = 0,
33 .reg_md_apsrc_0_sel = 0,
35 .reg_conn_apsrc_sel = 0,
39 .reg_spm_apsrc_req = 0,
41 .reg_spm_f26m_req = 0,
43 .reg_spm_infra_req = 0,
45 .reg_spm_vrf18_req = 0,
47 .reg_spm_ddr_en_req = 1,
49 .reg_spm_dvfs_req = 0,
51 .reg_spm_sw_mailbox_req = 0,
53 .reg_spm_sspm_mailbox_req = 0,
55 .reg_spm_adsp_mailbox_req = 0,
57 .reg_spm_scp_mailbox_req = 0,
61 .reg_sspm_srcclkena_0_mask_b = 1,
63 .reg_sspm_infra_req_0_mask_b = 1,
65 .reg_sspm_apsrc_req_0_mask_b = 1,
67 .reg_sspm_vrf18_req_0_mask_b = 1,
69 .reg_sspm_ddr_en_0_mask_b = 1,
71 .reg_scp_srcclkena_mask_b = 1,
73 .reg_scp_infra_req_mask_b = 1,
75 .reg_scp_apsrc_req_mask_b = 1,
77 .reg_scp_vrf18_req_mask_b = 1,
79 .reg_scp_ddr_en_mask_b = 1,
81 .reg_audio_dsp_srcclkena_mask_b = 1,
83 .reg_audio_dsp_infra_req_mask_b = 1,
85 .reg_audio_dsp_apsrc_req_mask_b = 1,
87 .reg_audio_dsp_vrf18_req_mask_b = 1,
89 .reg_audio_dsp_ddr_en_mask_b = 1,
91 .reg_apu_srcclkena_mask_b = 1,
93 .reg_apu_infra_req_mask_b = 1,
95 .reg_apu_apsrc_req_mask_b = 1,
97 .reg_apu_vrf18_req_mask_b = 1,
99 .reg_apu_ddr_en_mask_b = 1,
101 .reg_cpueb_srcclkena_mask_b = 1,
103 .reg_cpueb_infra_req_mask_b = 1,
105 .reg_cpueb_apsrc_req_mask_b = 1,
107 .reg_cpueb_vrf18_req_mask_b = 1,
109 .reg_cpueb_ddr_en_mask_b = 1,
111 .reg_bak_psri_srcclkena_mask_b = 0,
113 .reg_bak_psri_infra_req_mask_b = 0,
115 .reg_bak_psri_apsrc_req_mask_b = 0,
117 .reg_bak_psri_vrf18_req_mask_b = 0,
119 .reg_bak_psri_ddr_en_mask_b = 0,
123 .reg_msdc0_srcclkena_mask_b = 1,
125 .reg_msdc0_infra_req_mask_b = 1,
127 .reg_msdc0_apsrc_req_mask_b = 1,
129 .reg_msdc0_vrf18_req_mask_b = 1,
131 .reg_msdc0_ddr_en_mask_b = 1,
133 .reg_msdc1_srcclkena_mask_b = 1,
135 .reg_msdc1_infra_req_mask_b = 1,
137 .reg_msdc1_apsrc_req_mask_b = 1,
139 .reg_msdc1_vrf18_req_mask_b = 1,
141 .reg_msdc1_ddr_en_mask_b = 1,
143 .reg_msdc2_srcclkena_mask_b = 1,
145 .reg_msdc2_infra_req_mask_b = 1,
147 .reg_msdc2_apsrc_req_mask_b = 1,
149 .reg_msdc2_vrf18_req_mask_b = 1,
151 .reg_msdc2_ddr_en_mask_b = 1,
153 .reg_ufs_srcclkena_mask_b = 1,
155 .reg_ufs_infra_req_mask_b = 1,
157 .reg_ufs_apsrc_req_mask_b = 1,
159 .reg_ufs_vrf18_req_mask_b = 1,
161 .reg_ufs_ddr_en_mask_b = 1,
163 .reg_usb_srcclkena_mask_b = 1,
165 .reg_usb_infra_req_mask_b = 1,
167 .reg_usb_apsrc_req_mask_b = 1,
169 .reg_usb_vrf18_req_mask_b = 1,
171 .reg_usb_ddr_en_mask_b = 1,
173 .reg_pextp_p0_srcclkena_mask_b = 1,
175 .reg_pextp_p0_infra_req_mask_b = 1,
177 .reg_pextp_p0_apsrc_req_mask_b = 1,
179 .reg_pextp_p0_vrf18_req_mask_b = 1,
181 .reg_pextp_p0_ddr_en_mask_b = 1,
185 .reg_pextp_p1_srcclkena_mask_b = 1,
187 .reg_pextp_p1_infra_req_mask_b = 1,
189 .reg_pextp_p1_apsrc_req_mask_b = 1,
191 .reg_pextp_p1_vrf18_req_mask_b = 1,
193 .reg_pextp_p1_ddr_en_mask_b = 1,
195 .reg_gce0_infra_req_mask_b = 1,
197 .reg_gce0_apsrc_req_mask_b = 1,
199 .reg_gce0_vrf18_req_mask_b = 1,
201 .reg_gce0_ddr_en_mask_b = 1,
203 .reg_gce1_infra_req_mask_b = 1,
205 .reg_gce1_apsrc_req_mask_b = 1,
207 .reg_gce1_vrf18_req_mask_b = 1,
209 .reg_gce1_ddr_en_mask_b = 1,
211 .reg_spm_srcclkena_reserved_mask_b = 1,
213 .reg_spm_infra_req_reserved_mask_b = 1,
215 .reg_spm_apsrc_req_reserved_mask_b = 1,
217 .reg_spm_vrf18_req_reserved_mask_b = 1,
219 .reg_spm_ddr_en_reserved_mask_b = 1,
221 .reg_disp0_apsrc_req_mask_b = 1,
223 .reg_disp0_ddr_en_mask_b = 1,
225 .reg_disp1_apsrc_req_mask_b = 1,
227 .reg_disp1_ddr_en_mask_b = 1,
229 .reg_disp2_apsrc_req_mask_b = 1,
231 .reg_disp2_ddr_en_mask_b = 1,
233 .reg_disp3_apsrc_req_mask_b = 1,
235 .reg_disp3_ddr_en_mask_b = 1,
237 .reg_infrasys_apsrc_req_mask_b = 0,
239 .reg_infrasys_ddr_en_mask_b = 1,
242 .reg_cg_check_srcclkena_mask_b = 1,
244 .reg_cg_check_apsrc_req_mask_b = 1,
246 .reg_cg_check_vrf18_req_mask_b = 1,
248 .reg_cg_check_ddr_en_mask_b = 1,
252 .reg_mcusys_merge_apsrc_req_mask_b = 0x17,
254 .reg_mcusys_merge_ddr_en_mask_b = 0x17,
256 .reg_dramc_md32_infra_req_mask_b = 0,
258 .reg_dramc_md32_vrf18_req_mask_b = 0,
260 .reg_dramc_md32_ddr_en_mask_b = 0,
262 .reg_dvfsrc_event_trigger_mask_b = 1,
266 .reg_sc_sw2spm_wakeup_mask_b = 0,
268 .reg_sc_adsp2spm_wakeup_mask_b = 0,
270 .reg_sc_sspm2spm_wakeup_mask_b = 0,
272 .reg_sc_scp2spm_wakeup_mask_b = 0,
274 .reg_csyspwrup_ack_mask = 0,
276 .reg_csyspwrup_req_mask = 1,
280 .reg_wakeup_event_mask = 0xC1382213,
284 .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
500 bool first_load_fw =
true;
505 first_load_fw =
false;
507 if (!first_load_fw) {
545 dmem_words = total_words - pmem_words;
550 __func__, (
long)ptr, pmem_words, dmem_words);
615 ISRM_RET_IRQ_AUX_BF, 0x3ff);
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
#define assert(statement)
void spm_parse_firmware(struct mtk_mcu *mcu)
#define printk(level,...)
#define setbits32(addr, set)
#define SET32_BITFIELDS(addr,...)
#define clrsetbits32(addr, clear, set)
#define REGION_SIZE(name)
static void stopwatch_init(struct stopwatch *sw)
static long stopwatch_duration_msecs(struct stopwatch *sw)
#define BIOS_INFO
BIOS_INFO - Expected events.
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_ERR
BIOS_ERR - System in incomplete state.
int mtk_init_mcu(struct mtk_mcu *mcu)
static struct mtk_spm_regs *const mtk_spm
#define SPM_WAKEUP_EVENT_MASK_DEF
#define SPM_REGWR_CFG_KEY
#define POWER_ON_VAL1_DEF
#define SPM_FLAG_DISABLE_VCORE_DVS
#define REG_MD32_APB_INTERNAL_EN_LSB
#define ARMPLL_CLK_SEL_DEF
#define RG_PCM_WDT_WAKE_LSB
#define MD32PCM_DMA0_START_VAL
#define SPM_RESOURCE_ACK_CON0_DEF
#define SPM_BUS_PROTECT2_MASK_B_DEF
#define MD32PCM_DMA0_CON_VAL
#define SPM_FLAG_DISABLE_VCORE_DFS
#define SPM_RESOURCE_ACK_CON2_DEF
#define MD32PCM_CFGREG_SW_RSTN_RUN
#define SPM_RESOURCE_ACK_CON1_DEF
#define SPM_RESOURCE_ACK_CON3_DEF
#define SPM_WAKEUP_EVENT_MASK_BIT0
#define SPM_SYSCLK_SETTLE
#define SPM_BUS_PROTECT_MASK_B_DEF
#define RG_PCM_TIMER_EN_LSB
#define RG_AHBMIF_APBEN_LSB
#define SPM_DVS_DFS_LEVEL_DEF
#define SPM_FLAG_RUN_COMMON_SCENARIO
#define SPM_DVFS_LEVEL_DEF
#define SYS_TIMER_START_EN_LSB
#define REG_EVENT_LOCK_EN_LSB
#define REG_SPM_SRAM_ISOINT_B_LSB
#define SPM_EVENT_COUNTER_CLR_LSB
#define SPM_DVFSRC_ENABLE_LSB
#define SPM_DVFS_FORCE_ENABLE_LSB
#define MD32PCM_CFGREG_SW_RSTN_RESET
#define REG_SYSCLK1_SRC_MD2_SRCCLKENA
static void spm_code_swapping(void)
static void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
static void reset_spm(struct mtk_mcu *mcu)
static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl)
static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm)
static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl)
static void spm_init_pcm_register(void)
static void spm_reset_and_init_pcm(void)
static void spm_set_sysclk_settle(void)
static void spm_register_init(void)
static void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
static struct mtk_mcu spm
#define SPM_SYSTEM_BASE_OFFSET
static const struct pwr_ctrl spm_init_ctrl
const char * firmware_name
uint32_t spm_bus_protect_mask_b
uint32_t spm_resource_ack_con2
uint32_t spm_resource_ack_con1
u32 md32pcm_cfgreg_sw_rstn
uint32_t spm_bus_protect2_mask_b
uint32_t spm_dvs_dfs_level
u32 spm_wakeup_event_ext_mask
uint32_t spm_resource_ack_con0
u32 spm_wakeup_event_mask
uint32_t spm_resource_ack_con3
u8 reg_infrasys_ddr_en_mask_b
uint8_t reg_pextp_p1_ddr_en_mask_b
uint8_t reg_bak_psri_apsrc_req_mask_b
uint8_t reg_msdc1_infra_req_mask_b
uint8_t reg_apu_vrf18_req_mask_b
uint8_t reg_apu_infra_req_mask_b
uint8_t reg_gce0_infra_req_mask_b
uint8_t reg_ufs_infra_req_mask_b
uint8_t reg_msdc0_vrf18_req_mask_b
uint8_t reg_ufs_srcclkena_mask_b
uint8_t reg_sspm_srcclkena_0_mask_b
uint8_t reg_msdc2_srcclkena_mask_b
uint8_t reg_disp3_apsrc_req_mask_b
uint8_t reg_disp1_apsrc_req_mask_b
uint8_t reg_pextp_p1_apsrc_req_mask_b
uint8_t reg_ufs_apsrc_req_mask_b
uint8_t reg_gce1_apsrc_req_mask_b
uint8_t reg_scp_infra_req_mask_b
uint8_t reg_msdc0_srcclkena_mask_b
uint8_t reg_disp2_apsrc_req_mask_b
uint32_t pcm_flags_cust_set
uint8_t reg_msdc2_apsrc_req_mask_b
uint8_t reg_audio_dsp_apsrc_req_mask_b
uint8_t reg_spm_vrf18_req
u8 reg_msdc2_ddr_en_mask_b
uint8_t reg_msdc2_vrf18_req_mask_b
uint8_t reg_pextp_p1_vrf18_req_mask_b
uint8_t reg_msdc0_infra_req_mask_b
uint8_t reg_disp3_ddr_en_mask_b
u8 reg_disp0_ddr_en_mask_b
uint8_t reg_gce0_apsrc_req_mask_b
uint32_t reg_wakeup_event_mask
uint8_t reg_scp_vrf18_req_mask_b
uint8_t reg_gce1_ddr_en_mask_b
uint8_t reg_apu_srcclkena_mask_b
u8 reg_spm_apsrc_req_reserved_mask_b
uint8_t reg_md_apsrc_1_sel
uint8_t reg_msdc2_infra_req_mask_b
uint8_t reg_cpueb_ddr_en_mask_b
uint8_t reg_sspm_infra_req_0_mask_b
u8 reg_disp1_ddr_en_mask_b
uint8_t reg_bak_psri_vrf18_req_mask_b
uint8_t reg_apu_apsrc_req_mask_b
uint8_t reg_usb_ddr_en_mask_b
uint8_t reg_gce1_vrf18_req_mask_b
uint8_t reg_cpueb_infra_req_mask_b
uint32_t pcm_flags_cust_clr
uint8_t reg_conn_apsrc_sel
uint8_t reg_spm_adsp_mailbox_req
uint8_t reg_audio_dsp_infra_req_mask_b
uint8_t reg_cpueb_vrf18_req_mask_b
uint8_t reg_pextp_p1_srcclkena_mask_b
uint8_t reg_infrasys_apsrc_req_mask_b
uint8_t reg_mp1_cputop_idle_mask
uint8_t reg_audio_dsp_vrf18_req_mask_b
uint8_t reg_usb_infra_req_mask_b
u8 reg_msdc0_ddr_en_mask_b
uint8_t reg_pextp_p1_infra_req_mask_b
uint8_t reg_bak_psri_srcclkena_mask_b
u8 reg_bak_psri_ddr_en_mask_b
uint8_t reg_pextp_p0_srcclkena_mask_b
uint8_t reg_usb_apsrc_req_mask_b
uint8_t reg_msdc1_vrf18_req_mask_b
uint8_t reg_pextp_p0_ddr_en_mask_b
u8 reg_spm_vrf18_req_reserved_mask_b
uint8_t reg_msdc1_apsrc_req_mask_b
uint8_t reg_md_apsrc_0_sel
uint8_t reg_mcusys_idle_mask
uint8_t reg_usb_vrf18_req_mask_b
uint8_t reg_spm_sspm_mailbox_req
uint8_t reg_scp_apsrc_req_mask_b
uint8_t reg_usb_srcclkena_mask_b
uint8_t reg_gce0_vrf18_req_mask_b
uint8_t reg_pextp_p0_infra_req_mask_b
uint8_t reg_sspm_vrf18_req_0_mask_b
uint8_t reg_gce1_infra_req_mask_b
u8 reg_spm_ddr_en_reserved_mask_b
uint8_t reg_ufs_vrf18_req_mask_b
u8 reg_spm_srcclkena_reserved_mask_b
u8 reg_spm_infra_req_reserved_mask_b
uint32_t pcm_flags1_cust_set
uint32_t pcm_flags1_cust_clr
uint8_t reg_disp2_ddr_en_mask_b
uint8_t reg_msdc1_srcclkena_mask_b
u8 reg_audio_dsp_ddr_en_mask_b
uint8_t reg_pextp_p0_vrf18_req_mask_b
uint32_t reg_ext_wakeup_event_mask
uint8_t reg_cpueb_apsrc_req_mask_b
uint8_t reg_msdc0_apsrc_req_mask_b
uint8_t reg_sspm_apsrc_req_0_mask_b
uint8_t reg_scp_srcclkena_mask_b
uint8_t reg_bak_psri_infra_req_mask_b
uint8_t reg_spm_sw_mailbox_req
uint8_t reg_spm_infra_req
uint8_t reg_spm_apsrc_req
uint8_t reg_sspm_ddr_en_0_mask_b
u8 reg_msdc1_ddr_en_mask_b
uint8_t reg_cpueb_srcclkena_mask_b
uint8_t reg_gce0_ddr_en_mask_b
uint8_t reg_audio_dsp_srcclkena_mask_b
uint8_t reg_pextp_p0_apsrc_req_mask_b
uint8_t reg_spm_scp_mailbox_req
uint8_t reg_mp0_cputop_idle_mask