coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smihandler.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
console/console.h
>
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#include <
cpu/x86/smm.h
>
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#include <soc/nvs.h>
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#include <
southbridge/intel/bd82x6x/pch.h
>
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#include <
southbridge/intel/bd82x6x/me.h
>
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#include <
southbridge/intel/common/pmutil.h
>
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#include <
southbridge/intel/common/pmbase.h
>
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#include <
northbridge/intel/sandybridge/sandybridge.h
>
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#include <
ec/compal/ene932/ec.h
>
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#include "
ec.h
"
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static
u8
mainboard_smi_ec
(
void
)
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{
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u8
src;
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ec_kbc_write_cmd
(0x56);
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src =
ec_kbc_read_ob
();
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printk
(
BIOS_DEBUG
,
"%s src: %x\n"
, __func__, src);
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switch
(src) {
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case
EC_BATTERY_CRITICAL
:
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break
;
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case
EC_LID_CLOSE
:
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printk
(
BIOS_DEBUG
,
"LID CLOSED, SHUTDOWN\n"
);
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/* Go to S5 */
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write_pmbase32
(
PM1_CNT
,
read_pmbase32
(
PM1_CNT
) | (0xf << 10));
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break
;
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}
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return
src;
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}
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void
mainboard_smi_gpi
(
u32
gpi_sts)
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{
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if
(gpi_sts & (1 <<
EC_SMI_GPI
)) {
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/* Process all pending events from EC */
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do
{}
while
(
mainboard_smi_ec
() !=
EC_NO_EVENT
);
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}
else
if
(gpi_sts & (1 <<
EC_LID_GPI
)) {
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printk
(
BIOS_DEBUG
,
"LID CLOSED, SHUTDOWN\n"
);
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/* Go to S5 */
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write_pmbase32
(
PM1_CNT
,
read_pmbase32
(
PM1_CNT
) | (0xf << 10));
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}
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}
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void
mainboard_smi_sleep
(
u8
slp_typ)
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{
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/* Disable SCI and SMI events */
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/* Clear pending events that may trigger immediate wake */
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/* Enable wake events */
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/* Tell the EC to Disable USB power */
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if
(
gnvs
->
s3u0
== 0 &&
gnvs
->
s3u1
== 0) {
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ec_kbc_write_cmd
(0x45);
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ec_kbc_write_ib
(0xF2);
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}
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}
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int
mainboard_smi_apmc
(
u8
apmc)
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{
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switch
(apmc) {
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case
APM_CNT_ACPI_ENABLE
:
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/* Clear all pending events */
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/* EC cmd:59 data:E8 */
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ec_kbc_write_cmd
(0x59);
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ec_kbc_write_ib
(0xE8);
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/* Set LID GPI to generate SCIs */
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gpi_route_interrupt
(
EC_LID_GPI
,
GPI_IS_SCI
);
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break
;
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case
APM_CNT_ACPI_DISABLE
:
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/* Clear all pending events */
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/* EC cmd:59 data:e9 */
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ec_kbc_write_cmd
(0x59);
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ec_kbc_write_ib
(0xE9);
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/* Set LID GPI to generate SMIs */
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gpi_route_interrupt
(
EC_LID_GPI
,
GPI_IS_SMI
);
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break
;
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}
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return
0;
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}
PM1_CNT
#define PM1_CNT
Definition:
pm.h:27
printk
#define printk(level,...)
Definition:
stdlib.h:16
console.h
mainboard_smi_sleep
void __weak mainboard_smi_sleep(u8 slp_typ)
Definition:
smihandler.c:210
mainboard_smi_apmc
int __weak mainboard_smi_apmc(u8 data)
Definition:
smihandler.c:209
mainboard_smi_gpi
void __weak mainboard_smi_gpi(u32 gpi_sts)
Definition:
smihandler.c:208
ec_kbc_read_ob
u8 ec_kbc_read_ob(void)
Definition:
ec.c:71
ec_kbc_write_ib
void ec_kbc_write_ib(u8 data)
Definition:
ec.c:83
ec_kbc_write_cmd
void ec_kbc_write_cmd(u8 cmd)
Definition:
ec.c:77
ec.h
smm.h
APM_CNT_ACPI_DISABLE
#define APM_CNT_ACPI_DISABLE
Definition:
smm.h:21
APM_CNT_ACPI_ENABLE
#define APM_CNT_ACPI_ENABLE
Definition:
smm.h:22
BIOS_DEBUG
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition:
loglevel.h:128
EC_SMI_GPI
#define EC_SMI_GPI
Definition:
ec.h:10
EC_LID_GPI
#define EC_LID_GPI
Definition:
ec.h:8
EC_BATTERY_CRITICAL
#define EC_BATTERY_CRITICAL
Definition:
ec.h:28
EC_LID_CLOSE
#define EC_LID_CLOSE
Definition:
ec.h:21
EC_NO_EVENT
#define EC_NO_EVENT
Definition:
ec.h:13
mainboard_smi_ec
static u8 mainboard_smi_ec(void)
Definition:
smihandler.c:14
GPI_IS_SMI
#define GPI_IS_SMI
Definition:
smihandler.c:34
GPI_IS_SCI
#define GPI_IS_SCI
Definition:
smihandler.c:35
ec.h
read_pmbase32
u32 read_pmbase32(const u8 addr)
Definition:
pmbase.c:57
write_pmbase32
void write_pmbase32(const u8 addr, const u32 val)
Definition:
pmbase.c:36
pmbase.h
pmutil.h
sandybridge.h
gnvs
struct global_nvs * gnvs
Definition:
smm_module_handler.c:100
me.h
pch.h
gpi_route_interrupt
void gpi_route_interrupt(u8 gpi, u8 mode)
Definition:
smihandler.c:25
u32
uint32_t u32
Definition:
stdint.h:51
u8
uint8_t u8
Definition:
stdint.h:45
global_nvs::s3u0
u8 s3u0
Definition:
nvs.h:34
global_nvs::s3u1
u8 s3u1
Definition:
nvs.h:35
src
mainboard
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parrot
smihandler.c
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