#include <device/mmio.h>
#include <assert.h>
#include <console/console.h>
#include <delay.h>
#include <soc/addressmap.h>
#include <soc/clk_rst.h>
#include <soc/clock.h>
#include <soc/clst_clk.h>
#include <soc/console_uart.h>
#include <soc/flow.h>
#include <soc/maincpu.h>
#include <soc/pmc.h>
#include <soc/sysctr.h>

Include dependency graph for clock.c:

Data Structures
struct	pll_reg_info

struct	pll_fields

Macros
#define	PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco) {.n = _n, .m = _m, .p = _p, .kcp = _kcp, .kvco = _kvco,}

#define	PLL_NO_KCP_KVCO(_n, _m, _p) {.n = _n, .m = _m, .p = _p,}

#define	PLLX(_n, _m, _p, _kcp, _kvco) [PLLX_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)

#define	PLLC(_n, _m, _p) [PLLC_INDEX] = PLL_NO_KCP_KVCO(_n, _m, _p)

#define	PLLU(_n, _m, _p, _kcp, _kvco) [PLLU_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)

#define	PLLDP(_n, _m, _p, _kcp, _kvco) [PLLDP_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)

#define	PLLD(_n, _m, _p, _kcp, _kvco) [PLLD_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)

#define	SOR0_CLK_SEL0 (1 << 14)

#define	SOR0_CLK_SEL1 (1 << 15)

Enumerations
enum	{ PLLX_INDEX , PLLC_INDEX , PLLU_INDEX , PLLDP_INDEX , PLLD_INDEX , PLL_MAX_INDEX }

Functions
static u32	clock_get_osc_bits (void)

int	clock_get_osc_khz (void)

int	clock_get_pll_input_khz (void)

void	clock_init_arm_generic_timer (void)

void	sor_clock_stop (void)

void	sor_clock_start (void)

static void	init_pll (u32 index, u32 osc)

static void	init_pllc (u32 osc)

static void	init_pllu (u32 osc)

static void	init_utmip_pll (void)

static void	graphics_pll (void)

u32	clock_configure_plld (u32 frequency)

void	clock_early_uart (void)

void	clock_external_output (int clk_id)

void	clock_sdram (u32 m, u32 n, u32 p, u32 setup, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, u32 same_freq)

void	clock_halt_avp (void)

void	clock_init (void)

void	clock_grp_enable_clear_reset (u32 val, u32 clk_enb_set_reg, u32 rst_dev_clr_reg)

static void	clock_write_regs (u32 *const regs[DEV_CONFIG_BLOCKS], u32 bits[DEV_CONFIG_BLOCKS])

void	clock_enable_regs (u32 bits[DEV_CONFIG_BLOCKS])

void	clock_disable_regs (u32 bits[DEV_CONFIG_BLOCKS])

void	clock_set_reset_regs (u32 bits[DEV_CONFIG_BLOCKS])

void	clock_clr_reset_regs (u32 bits[DEV_CONFIG_BLOCKS])

void	clock_enable_clear_reset (u32 l, u32 h, u32 u, u32 v, u32 w, u32 x, u32 y)

static void	clock_reset_dev (u32 setaddr, u32 clraddr, u32 bit)

void	clock_reset_l (u32 bit)

void	clock_reset_h (u32 bit)

void	clock_reset_u (u32 bit)

void	clock_reset_v (u32 bit)

void	clock_reset_w (u32 bit)

void	clock_reset_x (u32 bit)

void	clock_reset_y (u32 bit)

void	clock_enable_audio (void)

Variables
static struct flow_ctlr *	flow = (void *)TEGRA_FLOW_BASE

static struct tegra_pmc_regs *	pmc = (void *)TEGRA_PMC_BASE

static struct sysctr_regs *	sysctr = (void *)TEGRA_SYSCTR0_BASE

struct pll_reg_info	pll_reg_table []

struct {
int khz

struct pll_fields plls [PLL_MAX_INDEX]

}	osc_table [16]

static u32 *const	clk_enb_set_arr [DEV_CONFIG_BLOCKS]

static u32 *const	clk_enb_clr_arr [DEV_CONFIG_BLOCKS]

static u32 *const	rst_dev_set_arr [DEV_CONFIG_BLOCKS]

static u32 *const	rst_dev_clr_arr [DEV_CONFIG_BLOCKS]

Macro Definition Documentation

◆ PLL_HAS_KCP_KVCO

#define PLL_HAS_KCP_KVCO	(	_n,
		_m,
		_p,
		_kcp,
		_kvco
	)	{.n = _n, .m = _m, .p = _p, .kcp = _kcp, .kvco = _kvco,}

Definition at line 92 of file clock.c.

◆ PLL_NO_KCP_KVCO

#define PLL_NO_KCP_KVCO	(	_n,
		_m,
		_p
	)	{.n = _n, .m = _m, .p = _p,}

Definition at line 94 of file clock.c.

◆ PLLC

#define PLLC	(	_n,
		_m,
		_p
	)	[PLLC_INDEX] = PLL_NO_KCP_KVCO(_n, _m, _p)

Definition at line 99 of file clock.c.

◆ PLLD

#define PLLD	(	_n,
		_m,
		_p,
		_kcp,
		_kvco
	)	[PLLD_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)

Definition at line 105 of file clock.c.

◆ PLLDP

#define PLLDP	(	_n,
		_m,
		_p,
		_kcp,
		_kvco
	)	[PLLDP_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)

Definition at line 103 of file clock.c.

◆ PLLU

#define PLLU	(	_n,
		_m,
		_p,
		_kcp,
		_kvco
	)	[PLLU_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)

Definition at line 101 of file clock.c.

◆ PLLX

#define PLLX	(	_n,
		_m,
		_p,
		_kcp,
		_kvco
	)	[PLLX_INDEX] = PLL_HAS_KCP_KVCO(_n, _m, _p, _kcp, _kvco)

Definition at line 97 of file clock.c.

◆ SOR0_CLK_SEL0

#define SOR0_CLK_SEL0 (1 << 14)

Definition at line 233 of file clock.c.

◆ SOR0_CLK_SEL1

#define SOR0_CLK_SEL1 (1 << 15)

Definition at line 234 of file clock.c.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
PLLX_INDEX
PLLC_INDEX
PLLU_INDEX
PLLDP_INDEX
PLLD_INDEX
PLL_MAX_INDEX

Definition at line 21 of file clock.c.

Function Documentation

◆ clock_clr_reset_regs()

void clock_clr_reset_regs ( u32 bits[DEV_CONFIG_BLOCKS] )

Definition at line 707 of file clock.c.

References clock_write_regs(), and rst_dev_clr_arr.

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◆ clock_configure_plld()

u32 clock_configure_plld ( u32 frequency )

plld (fo) = vco >> p, where 500MHz < vco < 1000MHz = (cf * n) >> p, where 1MHz < cf < 6MHz = ((ref / m) * n) >> p

Iterate the possible values of p (3 bits, 2^7) to find out a minimum safe vco, then find best (m, n). since m has only 5 bits, we can iterate all possible values. Note Tegra1xx supports 11 bits for n, but our pll_fields has only 10 bits for n.

Note values undershoot or overshoot target output frequency may not work if the values are not in "safe" range by panel specification.

Definition at line 385 of file clock.c.

References BIOS_DEBUG, BIOS_ERR, BIOS_WARNING, CLK_RST_REG, clock_get_osc_bits(), clock_get_pll_input_khz(), init_pll(), m, pll_fields::m, mhz, pll_fields::n, osc_table, pll_fields::p, PLLD_INDEX, PLLD_MISC1_SETUP, PLLD_MISC_EN_SDM, PLLD_MISC_SDM_DIN, printk, and write32().

Referenced by dp_display_startup(), dsi_display_startup(), enable_plld(), and tegra_output_dsi_setup_clock().

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◆ clock_disable_regs()

void clock_disable_regs ( u32 bits[DEV_CONFIG_BLOCKS] )

Definition at line 697 of file clock.c.

References clk_enb_clr_arr, and clock_write_regs().

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◆ clock_early_uart()

void clock_early_uart ( void )

Definition at line 478 of file clock.c.

References CLK_DIVIDER, CLK_SOURCE_SHIFT, CLK_UART_DIV_OVERRIDE, console_uart_clk_rst_reg(), console_uart_clk_src_dev_id(), console_uart_clock_enable_clear_reset(), console_uart_get_id(), TEGRA_PLLP_KHZ, UART_ID_NONE, and write32().

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◆ clock_enable_audio()

void clock_enable_audio ( void )

Definition at line 772 of file clock.c.

References CLK_L_I2S1, CLK_L_I2S2, CLK_L_I2S3, CLK_L_SPDIF, CLK_V_AHUB, CLK_V_APB2APE, CLK_V_EXTPERIPH1, CLK_V_I2S4, CLK_V_I2S5, and clock_enable_clear_reset().

Referenced by setup_audio().

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◆ clock_enable_clear_reset()

void clock_enable_clear_reset	(	u32	l,
		u32	h,
		u32	u,
		u32	v,
		u32	w,
		u32	x,
		u32	y
	)

Definition at line 712 of file clock.c.

References clock_clr_reset, clock_enable(), IO_STABILIZATION_DELAY, pll_fields::u, udelay(), x, and y.

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◆ clock_enable_regs()

void clock_enable_regs ( u32 bits[DEV_CONFIG_BLOCKS] )

Definition at line 692 of file clock.c.

References clk_enb_set_arr, and clock_write_regs().

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◆ clock_external_output()

void clock_external_output ( int clk_id )

Definition at line 492 of file clock.c.

References BIOS_CRIT, tegra_pmc_regs::clk_out_cntrl, pmc, printk, and setbits32.

◆ clock_get_osc_bits()

static u32 clock_get_osc_bits ( void )

static

Definition at line 203 of file clock.c.

References CLK_RST_REG, OSC_FREQ_MASK, OSC_FREQ_SHIFT, and read32().

Referenced by clock_configure_plld(), clock_get_osc_khz(), clock_init(), and graphics_pll().

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◆ clock_get_osc_khz()

int clock_get_osc_khz ( void )

Definition at line 208 of file clock.c.

References clock_get_osc_bits(), and osc_table.

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◆ clock_get_pll_input_khz()

int clock_get_pll_input_khz ( void )

Definition at line 213 of file clock.c.

References CLK_RST_REG, OSC_FREQ_MASK, OSC_FREQ_SHIFT, OSC_PREDIV_MASK, OSC_PREDIV_SHIFT, osc_table, and read32().

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◆ clock_grp_enable_clear_reset()

void clock_grp_enable_clear_reset	(	u32	val,
		u32 *	clk_enb_set_reg,
		u32 *	rst_dev_clr_reg
	)

Definition at line 634 of file clock.c.

References IO_STABILIZATION_DELAY, udelay(), val, and write32().

Referenced by soc_configure_funits().

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◆ clock_halt_avp()

void clock_halt_avp ( void )

Definition at line 562 of file clock.c.

References flow, FLOW_EVENT_GIC_IRQ, FLOW_EVENT_JTAG, FLOW_EVENT_LIC_IRQ, FLOW_MODE_WAITEVENT, flow_ctlr::halt_cop_events, and write32().

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◆ clock_init()

void clock_init ( void )

Definition at line 571 of file clock.c.

References CCLK_BURST_POLICY_VAL, CLK_DIVIDER, CLK_M_DIVISOR_BY_2, CLK_M_DIVISOR_MASK, CLK_RST_REG, clock_get_osc_bits(), clrbits32, clrsetbits32, graphics_pll(), HCLK_DIVISOR_SHIFT, init_pll(), init_pllc(), init_pllu(), init_utmip_pll(), OSC_DRIVE_STRENGTH, tegra_pmc_regs::osc_edpd_over, OSC_XOFS_MASK, OSC_XOFS_SHIFT, PCLK_DIVISOR_SHIFT, PLL_OUT1_SHIFT, PLL_OUT2_SHIFT, PLL_OUT3_SHIFT, PLL_OUT4_SHIFT, PLL_OUT_CLKEN, PLL_OUT_OVR, PLL_OUT_RATIO_SHIFT, PLL_OUT_RSTN, PLLX_IDDQ_MASK, PLLX_INDEX, pmc, PMC_OSC_EDPD_OVER_XOFS_MASK, PMC_OSC_EDPD_OVER_XOFS_SHIFT, SCLK_RUN_SHIFT, SCLK_SOURCE_PLLC_OUT1, SCLK_SYS_STATE_RUN, SCLK_SYS_STATE_SHIFT, TEGRA_PLLC_KHZ, TEGRA_PLLP_KHZ, TEGRA_PLLP_OUT3_KHZ, TEGRA_TMRUS_BASE, TIMERUS_USEC_CFG, TIMERUS_USEC_CFG_19P2_CLK_M, and write32().

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◆ clock_init_arm_generic_timer()

void clock_init_arm_generic_timer ( void )

Definition at line 221 of file clock.c.

References sysctr_regs::cntcr, sysctr_regs::cntfid0, read32(), sysctr, SYSCTR_CNTCR_EN, SYSCTR_CNTCR_HDBG, TEGRA_CLK_M_KHZ, and write32().

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◆ clock_reset_dev()

static void clock_reset_dev	(	u32 *	setaddr,
		u32 *	clraddr,
		u32	bit
	)

static

Definition at line 722 of file clock.c.

References LOGIC_STABILIZATION_DELAY, udelay(), and write32().

Referenced by clock_reset_h(), clock_reset_l(), clock_reset_u(), clock_reset_v(), clock_reset_w(), clock_reset_x(), and clock_reset_y().

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◆ clock_reset_h()

void clock_reset_h ( u32 bit )

Definition at line 735 of file clock.c.

References CLK_RST_REG, and clock_reset_dev().

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◆ clock_reset_l()

void clock_reset_l ( u32 bit )

Definition at line 729 of file clock.c.

References CLK_RST_REG, and clock_reset_dev().

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◆ clock_reset_u()

void clock_reset_u ( u32 bit )

Definition at line 741 of file clock.c.

References CLK_RST_REG, and clock_reset_dev().

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◆ clock_reset_v()

void clock_reset_v ( u32 bit )

Definition at line 747 of file clock.c.

References CLK_RST_REG, and clock_reset_dev().

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◆ clock_reset_w()

void clock_reset_w ( u32 bit )

Definition at line 753 of file clock.c.

References CLK_RST_REG, and clock_reset_dev().

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◆ clock_reset_x()

void clock_reset_x ( u32 bit )

Definition at line 759 of file clock.c.

References CLK_RST_REG, and clock_reset_dev().

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◆ clock_reset_y()

void clock_reset_y ( u32 bit )

Definition at line 765 of file clock.c.

References CLK_RST_REG, and clock_reset_dev().

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◆ clock_sdram()

void clock_sdram	(	u32	m,
		u32	n,
		u32	p,
		u32	setup,
		u32	kvco,
		u32	kcp,
		u32	stable_time,
		u32	emc_source,
		u32	same_freq
	)

Definition at line 512 of file clock.c.

References base, CLK_H_EMC, CLK_H_MEM, CLK_RST_REG, CLK_SOURCE_EMC_MC_EMC_SAME_FREQ, clock_enable_clear_reset(), IO_STABILIZATION_DELAY, pll_fields::kcp, pll_fields::kvco, m, pll_fields::n, pll_fields::p, PLL_BASE_BYPASS, PLL_BASE_DIVM_SHIFT, PLL_BASE_DIVN_SHIFT, PLL_BASE_DIVP_SHIFT, PLL_BASE_ENABLE, PLL_BASE_LOCK, PLLCMX_BASE_DIVM_MASK, PLLCMX_BASE_DIVN_MASK, PLLM_BASE_DIVP_MASK, PLLM_EN_LCKDET, PLLM_MISC1_SETUP_SHIFT, PLLM_MISC2_KCP_SHIFT, PLLM_MISC2_KVCO_SHIFT, read32(), setbits32, udelay(), and write32().

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◆ clock_set_reset_regs()

void clock_set_reset_regs ( u32 bits[DEV_CONFIG_BLOCKS] )

Definition at line 702 of file clock.c.

References clock_write_regs(), and rst_dev_set_arr.

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◆ clock_write_regs()

static void clock_write_regs	(	u32 *const	regs[DEV_CONFIG_BLOCKS],
		u32	bits[DEV_CONFIG_BLOCKS]
	)

static

Definition at line 682 of file clock.c.

References DEV_CONFIG_BLOCKS, and write32().

Referenced by clock_clr_reset_regs(), clock_disable_regs(), clock_enable_regs(), and clock_set_reset_regs().

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◆ graphics_pll()

static void graphics_pll ( void )

static

Definition at line 356 of file clock.c.

References CLK_RST_REG, clock_get_osc_bits(), init_pll(), PLLDP_INDEX, and write32().

Referenced by clock_init().

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◆ init_pll()

static void init_pll	(	u32	index,
		u32	osc
	)

static

Definition at line 252 of file clock.c.

References assert, pll_reg_info::base_reg, pll_reg_info::kcp_kvco_reg, pll_reg_info::kcp_shift, pll_reg_info::kvco_shift, pll_reg_info::lock_enb_reg, pll_reg_info::lock_enb_val, pll_reg_info::m_shift, pll_reg_info::n_shift, osc_table, pll_reg_info::p_shift, PLL_BASE_BYPASS, PLL_BASE_ENABLE, pll_reg_info::pll_lock_reg, pll_reg_info::pll_lock_val, PLL_MAX_INDEX, pll_reg_table, read32(), setbits32, and write32().

Referenced by clock_configure_plld(), clock_init(), graphics_pll(), init_pllc(), and init_pllu().

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◆ init_pllc()

static void init_pllc ( u32 osc )

static

Definition at line 285 of file clock.c.

References CLK_RST_REG, clrbits32, init_pll(), PLLC_BASE_LOCK, PLLC_INDEX, PLLC_MISC_1_IDDQ, PLLC_MISC_RESET, and read32().

Referenced by clock_init().

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◆ init_pllu()

static void init_pllu ( u32 osc )

static

Definition at line 301 of file clock.c.

References CLK_RST_REG, clrbits32, init_pll(), PLLU_INDEX, PLLU_MISC_IDDQ, and udelay().

Referenced by clock_init().

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◆ init_utmip_pll()

static void init_utmip_pll ( void )

static

Definition at line 312 of file clock.c.

Referenced by clock_init().

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◆ sor_clock_start()

void sor_clock_start ( void )

Definition at line 246 of file clock.c.

References CLK_RST_REG, setbits32, and SOR0_CLK_SEL0.

◆ sor_clock_stop()

void sor_clock_stop ( void )

Definition at line 236 of file clock.c.

References CLK_RST_REG, clrbits32, SOR0_CLK_SEL0, and SOR0_CLK_SEL1.

Variable Documentation

◆ clk_enb_clr_arr

u32* const clk_enb_clr_arr[DEV_CONFIG_BLOCKS]

static

Initial value:

= {
        CLK_RST_REG(clk_enb_l_clr),
        CLK_RST_REG(clk_enb_h_clr),
        CLK_RST_REG(clk_enb_u_clr),
        CLK_RST_REG(clk_enb_v_clr),
        CLK_RST_REG(clk_enb_w_clr),
        CLK_RST_REG(clk_enb_x_clr),
        CLK_RST_REG(clk_enb_y_clr),
}

Definition at line 652 of file clock.c.

Referenced by clock_disable_regs().

◆ clk_enb_set_arr

u32* const clk_enb_set_arr[DEV_CONFIG_BLOCKS]

static

Initial value:

= {
        CLK_RST_REG(clk_enb_l_set),
        CLK_RST_REG(clk_enb_h_set),
        CLK_RST_REG(clk_enb_u_set),
        CLK_RST_REG(clk_enb_v_set),
        CLK_RST_REG(clk_enb_w_set),
        CLK_RST_REG(clk_enb_x_set),
        CLK_RST_REG(clk_enb_y_set),
}

Definition at line 642 of file clock.c.

Referenced by clock_enable_regs().

◆ flow

struct flow_ctlr* flow = (void *)TEGRA_FLOW_BASE

static

Definition at line 17 of file clock.c.

Referenced by clock_halt_avp().

◆ khz

int khz

Definition at line 131 of file clock.c.

◆

struct { ... } osc_table[16]

◆ pll_reg_table

struct pll_reg_info pll_reg_table[]

Referenced by init_pll().

◆ plls

struct pll_fields plls[PLL_MAX_INDEX]

Definition at line 131 of file clock.c.

◆ pmc

struct tegra_pmc_regs* pmc = (void *)TEGRA_PMC_BASE

static

Definition at line 18 of file clock.c.

Referenced by clock_external_output(), and clock_init().

◆ rst_dev_clr_arr

u32* const rst_dev_clr_arr[DEV_CONFIG_BLOCKS]

static

Initial value:

= {
        CLK_RST_REG(rst_dev_l_clr),
        CLK_RST_REG(rst_dev_h_clr),
        CLK_RST_REG(rst_dev_u_clr),
        CLK_RST_REG(rst_dev_v_clr),
        CLK_RST_REG(rst_dev_w_clr),
        CLK_RST_REG(rst_dev_x_clr),
        CLK_RST_REG(rst_dev_y_clr),
}

Definition at line 672 of file clock.c.

Referenced by clock_clr_reset_regs().

◆ rst_dev_set_arr

u32* const rst_dev_set_arr[DEV_CONFIG_BLOCKS]

static

Initial value:

= {
        CLK_RST_REG(rst_dev_l_set),
        CLK_RST_REG(rst_dev_h_set),
        CLK_RST_REG(rst_dev_u_set),
        CLK_RST_REG(rst_dev_v_set),
        CLK_RST_REG(rst_dev_w_set),
        CLK_RST_REG(rst_dev_x_set),
        CLK_RST_REG(rst_dev_y_set),
}

Definition at line 662 of file clock.c.

Referenced by clock_set_reset_regs().

◆ sysctr

struct sysctr_regs* sysctr = (void *)TEGRA_SYSCTR0_BASE

static

Definition at line 19 of file clock.c.

Referenced by clock_init_arm_generic_timer().

Data Structures

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ PLL_HAS_KCP_KVCO

◆ PLL_NO_KCP_KVCO

◆ PLLC

◆ PLLD

◆ PLLDP

◆ PLLU

◆ PLLX

◆ SOR0_CLK_SEL0

◆ SOR0_CLK_SEL1

Enumeration Type Documentation

◆ anonymous enum

Function Documentation

◆ clock_clr_reset_regs()

◆ clock_configure_plld()

◆ clock_disable_regs()

◆ clock_early_uart()

◆ clock_enable_audio()

◆ clock_enable_clear_reset()

◆ clock_enable_regs()

◆ clock_external_output()

◆ clock_get_osc_bits()

◆ clock_get_osc_khz()

◆ clock_get_pll_input_khz()

◆ clock_grp_enable_clear_reset()

◆ clock_halt_avp()

◆ clock_init()

◆ clock_init_arm_generic_timer()

◆ clock_reset_dev()

◆ clock_reset_h()

◆ clock_reset_l()

◆ clock_reset_u()

◆ clock_reset_v()

◆ clock_reset_w()

◆ clock_reset_x()

◆ clock_reset_y()

◆ clock_sdram()

◆ clock_set_reset_regs()

◆ clock_write_regs()

◆ graphics_pll()

◆ init_pll()

◆ init_pllc()

◆ init_pllu()

◆ init_utmip_pll()

◆ sor_clock_start()

◆ sor_clock_stop()

Variable Documentation

◆ clk_enb_clr_arr

◆ clk_enb_set_arr

◆ flow

◆ khz

◆

◆ pll_reg_table

◆ plls

◆ pmc

◆ rst_dev_clr_arr

◆ rst_dev_set_arr

◆ sysctr