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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/hpet.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <option.h>
#include <pc80/mc146818rtc.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include "chip.h"
#include "i82801dx.h"
Go to the source code of this file.
Macros | |
#define | NMI_OFF 0 |
Typedefs | |
typedef struct southbridge_intel_i82801dx_config | config_t |
Functions | |
static void | i82801dx_enable_acpi (struct device *dev) |
Enable ACPI I/O range. More... | |
static void | i82801dx_enable_ioapic (struct device *dev) |
Set miscellaneous static southbridge features. More... | |
static void | i82801dx_enable_serial_irqs (struct device *dev) |
static void | i82801dx_pirq_init (struct device *dev) |
static void | i82801dx_power_options (struct device *dev) |
static void | gpio_init (struct device *dev) |
static void | i82801dx_rtc_init (struct device *dev) |
static void | i82801dx_lpc_route_dma (struct device *dev, u8 mask) |
static void | i82801dx_lpc_decode_en (struct device *dev) |
static void | enable_hpet (struct device *dev) |
static void | lpc_init (struct device *dev) |
static void | i82801dx_lpc_read_resources (struct device *dev) |
Variables | |
static struct device_operations | lpc_ops |
static const struct pci_driver lpc_driver_db | __pci_driver |
typedef struct southbridge_intel_i82801dx_config config_t |
Definition at line 212 of file lpc.c.
References BIOS_DEBUG, BIOS_INFO, BIOS_WARNING, GEN_CNTL, HPET_BASE_ADDRESS, pci_read_config32(), pci_write_config32(), printk, and val.
Referenced by lpc_init().
Definition at line 156 of file lpc.c.
References GPIO_BASE, GPIO_CNTL, GPIOBASE_ADDR, pci_write_config32(), and pci_write_config8().
Referenced by lpc_init().
Enable ACPI I/O range.
dev | PCI device with ACPI and PM BAR's |
Definition at line 27 of file lpc.c.
References ACPI_CNTL, ACPI_EN, pci_write_config32(), pci_write_config8(), PMBASE, and PMBASE_ADDR.
Referenced by lpc_init().
Set miscellaneous static southbridge features.
dev | PCI device with I/O APIC control registers |
Definition at line 41 of file lpc.c.
References BIOS_DEBUG, GEN_CNTL, ioapic_set_boot_config(), pci_read_config32(), pci_write_config32(), printk, setup_ioapic(), and VIO_APIC_VADDR.
Referenced by lpc_init().
Definition at line 58 of file lpc.c.
References pci_write_config8(), and SERIRQ_CNTL.
Referenced by lpc_init().
Definition at line 198 of file lpc.c.
References COM_DEC, LPC_EN, pci_write_config16(), and pci_write_config8().
Referenced by lpc_init().
Definition at line 183 of file lpc.c.
References mask, PCI_DMA_CFG, pci_read_config16(), and pci_write_config16().
Referenced by lpc_init().
Definition at line 67 of file lpc.c.
References device::chip_info, config, pci_write_config8(), PIRQA_ROUT, PIRQB_ROUT, PIRQC_ROUT, PIRQD_ROUT, PIRQE_ROUT, PIRQF_ROUT, PIRQG_ROUT, and PIRQH_ROUT.
Referenced by lpc_init().
Definition at line 82 of file lpc.c.
References BIOS_INFO, GEN_PMCON_1, GEN_PMCON_3, get_uint_option(), inb(), inl(), MAINBOARD_POWER_KEEP, MAINBOARD_POWER_OFF, MAINBOARD_POWER_ON, NMI_OFF, outb(), outl(), pci_read_config16(), pci_read_config8(), pci_write_config16(), pci_write_config8(), pmbase, and printk.
Referenced by lpc_init().
Definition at line 163 of file lpc.c.
References cmos_init(), GEN_PMCON_3, GEN_STS, pci_read_config32(), pci_read_config8(), pci_write_config8(), RTC_BATTERY_DEAD, RTC_CONF, and rtc_failed().
Referenced by lpc_init().
Definition at line 246 of file lpc.c.
References aseg_smm_lock(), CONFIG, enable_hpet(), gpio_init(), i82801dx_enable_acpi(), i82801dx_enable_ioapic(), i82801dx_enable_serial_irqs(), i82801dx_lpc_decode_en(), i82801dx_lpc_route_dma(), i82801dx_pirq_init(), i82801dx_power_options(), i82801dx_rtc_init(), isa_dma_init(), and setup_i8259().
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