coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <types.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <commonlib/region.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <soc/nvs.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <southbridge/intel/common/gpio.h>
#include <cpu/intel/model_206ax/model_206ax.h>
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/finalize.h>
#include "pch.h"
Go to the source code of this file.
Macros | |
#define | IOTRAP(x) (trap_sts & (1 << x)) |
Functions | |
int | southbridge_io_trap_handler (int smif) |
static void | southbridge_gate_memory_reset_real (int offset, u16 use, u16 io, u16 lvl) |
void | southbridge_gate_memory_reset (void) |
void | southbridge_smi_monitor (void) |
static void | xhci_a0_suspend_smm_workaround (void) |
void | southbridge_smm_xhci_sleep (u8 slp_type) |
void | southbridge_finalize_all (void) |
Definition at line 215 of file smihandler.c.
References intel_me_finalize_smm(), intel_model_206ax_finalize_smm(), intel_pch_finalize_smm(), and intel_sandybridge_finalize_smm().
Referenced by southbridge_smi_apmc().
Definition at line 69 of file smihandler.c.
References GP_IO_SEL, GP_IO_SEL2, GP_LVL, GP_LVL2, GPIO_USE_SEL, GPIO_USE_SEL2, GPIOBASE, PCH_LPC_DEV, pci_read_config16(), and southbridge_gate_memory_reset_real().
Referenced by southbridge_smi_sleep().
Definition at line 38 of file smihandler.c.
References inl(), offset, and outl().
Referenced by southbridge_gate_memory_reset().
int southbridge_io_trap_handler | ( | int | smif | ) |
Definition at line 21 of file smihandler.c.
References BIOS_DEBUG, gnvs, printk, and global_nvs::smif.
Definition at line 89 of file smihandler.c.
References BIOS_DEBUG, gnvs, io_trap_handler(), IOTRAP, mask, printk, RCBA32, and global_nvs::smif.
Definition at line 182 of file smihandler.c.
References ACPI_S3, ACPI_S4, ACPI_S5, FD, PCH_DISABLE_XHCI, PCH_LPC_DEV, pch_silicon_type(), PCH_TYPE_PPT, PCH_XHCI_DEV, pci_or_config16(), pci_read_config32(), RCBA, RCBA32, RCBA_ENABLE, xhci_a0_suspend_smm_workaround(), and XHCI_PWR_CNTL_STS.
Referenced by southbridge_smi_sleep().
Definition at line 146 of file smihandler.c.
References KiB, pch_iobp_update(), pch_silicon_revision(), PCH_STEP_A0, PCH_XHCI_DEV, pci_and_config16(), PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_MEM_ATTR_MASK, PCI_COMMAND, PCI_COMMAND_MASTER, PCI_COMMAND_MEMORY, pci_or_config16(), pci_read_config32(), read32(), smm_points_to_smram(), XHCI_PORTSC_x_USB3, and XHCI_PWR_CNTL_STS.
Referenced by southbridge_smm_xhci_sleep().