17 #define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1)
18 #define KCS_DEV PNP_DEV(X9SCL_WPCM450_PNP_BASE, 0x11)
20 #define SUPERIO_INITVAL(reg, data) {(reg), (data)}
21 #define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x))
static __always_inline void pci_write_config16(const struct device *dev, u16 reg, u16 val)
void bootblock_mainboard_early_init(void)
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
const struct southbridge_usb_port mainboard_usb_ports[]
void mainboard_early_init(void)
static void superio_init(void)
#define SUPERIO_INITVAL(reg, data)
static void bmc_init(void)
static const uint8_t superio_initvals[][2]
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
#define PCI_DEV(SEGBUS, DEV, FN)
void pnp_set_logical_device(struct device *dev)
void pnp_set_enable(struct device *dev, int enable)
void pnp_set_iobase(struct device *dev, u8 index, u16 iobase)
void pnp_write_config(struct device *dev, u8 reg, u8 value)
#define PNP_DEV(PORT, FUNC)
#define X9SCL_NCT6776_HWM_BASE
#define X9SCL_WPCM450_KCS_BASE
#define X9SCL_NCT6776_PNP_BASE