coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
azalia.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/pci_ops.h>
8 #include <device/mmio.h>
9 #include <delay.h>
10 #include <device/azalia_device.h>
11 
12 #include "chip.h"
13 #include "pch.h"
14 
15 static int codec_detect(u8 *base)
16 {
17  u8 reg8;
18 
19  if (azalia_exit_reset(base) < 0)
20  goto no_codec;
21 
22  /* Write back the value once reset bit is set. */
24 
25  /* Read in Codec location (BAR + 0xe)[2..0] */
26  reg8 = read8(base + HDA_STATESTS_REG);
27  reg8 &= 0x0f;
28  if (!reg8)
29  goto no_codec;
30 
31  return reg8;
32 
33 no_codec:
34  /* Codec not found, put HDA back in reset */
36  printk(BIOS_DEBUG, "Azalia: No codec!\n");
37  return 0;
38 }
39 
40 static void azalia_init(struct device *dev)
41 {
42  u8 *base;
43  struct resource *res;
44  u32 codec_mask;
45  u32 reg32;
46 
48  if (!res)
49  return;
50 
51  // NOTE this will break as soon as the Azalia gets a bar above 4G.
52  // Is there anything we can do about it?
53  base = res2mmio(res, 0, 0);
54  printk(BIOS_DEBUG, "Azalia: base = %p\n", base);
55 
56  if (RCBA32(CIR31) & (1 << 31)) {
57  reg32 = pci_read_config32(dev, 0x120);
58  reg32 &= 0xf8ffff01;
59  reg32 |= (1 << 24); // 2 << 24 for server
60  reg32 |= RCBA32(CIR31) & 0xfe;
61  pci_write_config32(dev, 0x120, reg32);
62 
63  pci_or_config16(dev, 0x78, 1 << 11);
64  } else
65  printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
66 
67  pci_and_config32(dev, 0x114, ~0xfe);
68 
69  // Set VCi enable bit
70  pci_or_config32(dev, 0x120, 1 << 31);
71 
72  // Enable HDMI codec:
73  pci_or_config32(dev, 0xc4, 1 << 1);
74 
75  pci_or_config8(dev, 0x43, 1 << 6);
76 
77  /* Additional programming steps */
78  pci_or_config32(dev, 0xc4, 1 << 13);
79 
80  pci_or_config32(dev, 0xc4, 1 << 10);
81 
82  pci_and_config32(dev, 0xd0, ~(1 << 31));
83 
84  if (dev->device == 0x1e20) {
85  /* Additional step on Panther Point */
86  pci_or_config32(dev, 0xc4, 1 << 17);
87  }
88 
89  /* Set Bus Master */
91 
92  pci_write_config8(dev, 0x3c, 0x0a); // unused?
93 
94  /* Codec Initialization Programming Sequence */
95 
96  /* Take controller out of reset */
97  reg32 = read32(base + HDA_GCTL_REG);
98  reg32 |= HDA_GCTL_CRST;
99  write32(base + HDA_GCTL_REG, reg32);
100  /* Wait 1ms */
101  udelay(1000);
102 
103  // Select Azalia mode. This needs to be controlled via devicetree.cb
104  pci_or_config8(dev, 0x40, 1); // Audio Control
105 
106  // Docking not supported
107  pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
108 
109  codec_mask = codec_detect(base);
110 
111  if (codec_mask) {
112  printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
113  azalia_codecs_init(base, codec_mask);
114  }
115 
116  /* Enable dynamic clock gating */
117  pci_update_config8(dev, 0x43, ~0x07, (1 << 2) | (1 << 0));
118 }
119 
120 static const char *azalia_acpi_name(const struct device *dev)
121 {
122  return "HDEF";
123 }
124 
125 static struct device_operations azalia_ops = {
127  .set_resources = pci_dev_set_resources,
128  .enable_resources = pci_dev_enable_resources,
129  .init = azalia_init,
130  .ops_pci = &pci_dev_ops_pci,
131  .acpi_name = azalia_acpi_name,
132 };
133 
134 static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 };
135 
136 static const struct pci_driver pch_azalia __pci_driver = {
137  .ops = &azalia_ops,
138  .vendor = PCI_VID_INTEL,
139  .devices = pci_device_ids,
140 };
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
static uint16_t read16(const void *addr)
Definition: mmio.h:17
static uint32_t read32(const void *addr)
Definition: mmio.h:22
static uint8_t read8(const void *addr)
Definition: mmio.h:12
static void write16(void *addr, uint16_t val)
Definition: mmio.h:35
int azalia_enter_reset(u8 *base)
Definition: azalia_device.c:38
void azalia_codecs_init(u8 *base, u16 codec_mask)
int azalia_exit_reset(u8 *base)
Definition: azalia_device.c:44
#define HDA_GCTL_REG
Definition: azalia_device.h:12
#define HDA_GCTL_CRST
Definition: azalia_device.h:13
#define HDA_STATESTS_REG
Definition: azalia_device.h:14
#define HDA_GCAP_REG
Definition: azalia_device.h:11
static const char * azalia_acpi_name(const struct device *dev)
Definition: azalia.c:120
static int codec_detect(u8 *base)
Definition: azalia.c:15
static const unsigned short pci_device_ids[]
Definition: azalia.c:134
static void azalia_init(struct device *dev)
Definition: azalia.c:40
static struct device_operations azalia_ops
Definition: azalia.c:125
static const struct pci_driver pch_azalia __pci_driver
Definition: azalia.c:136
#define printk(level,...)
Definition: stdlib.h:16
struct resource * probe_resource(const struct device *dev, unsigned int index)
See if a resource structure already exists for a given index.
Definition: device_util.c:323
static __always_inline void pci_or_config32(const struct device *dev, u16 reg, u32 ormask)
Definition: pci_ops.h:191
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition: pci_ops.h:76
static __always_inline void pci_and_config8(const struct device *dev, u16 reg, u8 andmask)
Definition: pci_ops.h:136
static __always_inline void pci_update_config8(const struct device *dev, u16 reg, u8 mask, u8 or)
Definition: pci_ops.h:88
static __always_inline void pci_or_config16(const struct device *dev, u16 reg, u16 ormask)
Definition: pci_ops.h:180
static __always_inline void pci_or_config8(const struct device *dev, u16 reg, u8 ormask)
Definition: pci_ops.h:169
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
static __always_inline void pci_and_config32(const struct device *dev, u16 reg, u32 andmask)
Definition: pci_ops.h:158
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val)
Definition: pci_ops.h:64
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define PCI_COMMAND_MASTER
Definition: pci_def.h:13
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
#define PCI_COMMAND
Definition: pci_def.h:10
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
void pci_dev_read_resources(struct device *dev)
Definition: pci_device.c:534
struct pci_operations pci_dev_ops_pci
Default device operation for PCI devices.
Definition: pci_device.c:911
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
static void * res2mmio(const struct resource *res, unsigned long offset, unsigned long mask)
Definition: resource.h:87
uintptr_t base
Definition: uart.c:17
#define CIR31
Definition: pch.h:245
#define RCBA32(x)
Definition: rcba.h:14
uint32_t u32
Definition: stdint.h:51
uint8_t u8
Definition: stdint.h:45
void(* read_resources)(struct device *dev)
Definition: device.h:39
Definition: device.h:107
unsigned int device
Definition: device.h:117
void udelay(uint32_t us)
Definition: udelay.c:15