coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
early_init.c
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/hpet.h>
4 #include <bootblock_common.h>
5 #include <stdint.h>
6 #include <arch/io.h>
13 
14 #define SIO_PORT 0x164e
15 
17 {
18  const u16 port = SIO_PORT;
19  const u16 runtime_port = 0x180;
20 
22 
23  /* Turn on configuration mode. */
24  outb(0x55, port);
25 
26  /* Set the GPIO direction, polarity, and type. */
27  sio1007_setreg(port, 0x31, 1 << 0, 1 << 0);
28  sio1007_setreg(port, 0x32, 0 << 0, 1 << 0);
29  sio1007_setreg(port, 0x33, 0 << 0, 1 << 0);
30 
31  /* Set the base address for the runtime register block. */
32  sio1007_setreg(port, 0x30, runtime_port >> 4, 0xff);
33  sio1007_setreg(port, 0x21, runtime_port >> 12, 0xff);
34 
35  /* Turn on address decoding for it. */
36  sio1007_setreg(port, 0x3a, 1 << 1, 1 << 1);
37 
38  /* Set the value of GPIO 10 by changing GP1, bit 0. */
39  u8 byte;
40  byte = inb(runtime_port + 0xc);
41  byte |= (1 << 0);
42  outb(byte, runtime_port + 0xc);
43 
44  /* Turn off address decoding for it. */
45  sio1007_setreg(port, 0x3a, 0 << 1, 1 << 1);
46 
47  /* Turn off configuration mode. */
48  outb(0xaa, port);
49 }
50 
52 {
53  struct pei_data pei_data_template = {
55  .mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
56  .dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
57  .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
58  .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
59  .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
60  .wdbbar = 0x4000000,
61  .wdbsize = 0x1000,
62  .hpet_address = HPET_BASE_ADDRESS,
63  .rcba = (uintptr_t)DEFAULT_RCBA,
66  .thermalbase = 0xfed08000,
67  .system_type = 0, // 0 Mobile, 1 Desktop/Server
68  .tseg_size = CONFIG_SMM_TSEG_SIZE,
69  .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 },
70  .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
71  .ec_present = 0,
72  .max_ddr3_freq = 1600,
73  .usb_port_config = {
74  { 1, 0, 0x0040 }, /* P0: Front port (OC0) */
75  { 1, 1, 0x0040 }, /* P1: Back port (OC1) */
76  { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */
77  { 1, 0, 0x0040 }, /* P3: MMC (no OC) */
78  { 1, 2, 0x0040 }, /* P4: Front port (OC2) */
79  { 0, 0, 0x0000 }, /* P5: Empty */
80  { 0, 0, 0x0000 }, /* P6: Empty */
81  { 0, 0, 0x0000 }, /* P7: Empty */
82  { 1, 4, 0x0040 }, /* P8: Back port (OC4) */
83  { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */
84  { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */
85  { 0, 4, 0x0000 }, /* P11: Empty */
86  { 1, 6, 0x0040 }, /* P12: Back port (OC6) */
87  { 1, 5, 0x0040 }, /* P13: Back port (OC5) */
88  },
89  };
90  *pei_data = pei_data_template;
91 }
92 
94  /* enabled power USB oc pin */
95  { 1, 0, 0 }, /* P0: Front port (OC0) */
96  { 1, 0, 1 }, /* P1: Back port (OC1) */
97  { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
98  { 1, 0, -1 }, /* P3: MMC (no OC) */
99  { 1, 0, 2 }, /* P4: Front port (OC2) */
100  { 0, 0, -1 }, /* P5: Empty */
101  { 0, 0, -1 }, /* P6: Empty */
102  { 0, 0, -1 }, /* P7: Empty */
103  { 1, 0, 4 }, /* P8: Back port (OC4) */
104  { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */
105  { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */
106  { 0, 0, -1 }, /* P11: Empty */
107  { 1, 0, 6 }, /* P12: Back port (OC6) */
108  { 1, 0, 5 }, /* P13: Back port (OC5) */
109 };
110 
111 void mainboard_get_spd(spd_raw_data *spd, bool id_only)
112 {
113  read_spd(&spd[0], 0x50, id_only);
114  read_spd(&spd[2], 0x52, id_only);
115 }
116 
117 int mainboard_should_reset_usb(int s3resume)
118 {
119  return !s3resume;
120 }
#define HPET_BASE_ADDRESS
Definition: hpet.h:6
u8 inb(u16 port)
void outb(u8 val, u16 port)
port
Definition: i915.h:29
u8 spd_raw_data[256]
Definition: ddr3.h:156
#define DEFAULT_PMBASE
Definition: iomap.h:14
void bootblock_mainboard_early_init(void)
Definition: early_init.c:11
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
Definition: early_init.c:25
const struct southbridge_usb_port mainboard_usb_ports[]
Definition: early_init.c:8
void mainboard_fill_pei_data(struct pei_data *pei)
Definition: early_init.c:58
int mainboard_should_reset_usb(int s3resume)
Definition: early_init.c:53
#define SIO_PORT
Definition: early_init.c:14
#define PEI_VERSION
Definition: pei_data.h:9
void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
Definition: raminit.c:138
int sio1007_enable_uart_at(u16 port)
Definition: early_serial.c:18
void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask)
Definition: early_serial.c:7
#define DEFAULT_GPIOBASE
Definition: pch.h:22
#define DEFAULT_RCBA
Definition: rcba.h:6
static u16 pmbase
Definition: smi.c:27
unsigned long uintptr_t
Definition: stdint.h:21
uint16_t u16
Definition: stdint.h:48
uint8_t u8
Definition: stdint.h:45
uint8_t spd_addresses[4]
Definition: pei_data.h:60
uint32_t tseg_size
Definition: pei_data.h:59
uint32_t system_type
Definition: pei_data.h:58
uint32_t gpiobase
Definition: pei_data.h:55
uint32_t pei_version
Definition: pei_data.h:43
uint32_t thermalbase
Definition: pei_data.h:33