6 #include <soc/addressmap.h>
7 #include <soc/infracfg.h>
8 #include <soc/mcucfg.h>
57 #define MUX(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift) \
59 .reg = &mtk_topckgen->_reg, \
60 .mux_shift = _mux_shift, \
61 .mux_width = _mux_width, \
62 .upd_reg = &mtk_topckgen->_upd_reg, \
63 .upd_shift = _upd_shift, \
183 #define MMPLL_RSTB_SHIFT (23)
210 static const struct pll plls[] = {
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
void mux_set_sel(const struct mux *mux, u32 sel)
int pll_set_rate(const struct pll *pll, u32 rate)
#define setbits32(addr, set)
#define clrsetbits32(addr, clear, set)
#define clrbits32(addr, clear)
void mt_pll_raise_little_cpu_freq(u32 freq)
void pll_set_pcw_change(const struct pll *pll)
static struct mt8183_infracfg_regs *const mt8183_infracfg
static struct mt8183_mcucfg_regs *const mt8183_mcucfg
static const struct mux muxes[]
#define MUX(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)
static const struct rate rates[]
static const struct mux_sel mux_sels[]
static const struct pll plls[]
#define PLL(_id, _reg, _pwr_reg, _rstb, _pcwbits, _div_reg, _div_shift, _pcw_reg, _pcw_shift, _div_rate)