coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ehci.c File Reference
#include <acpi/acpi.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <reg_script.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/ehci.h>
#include "chip.h"
Include dependency graph for ehci.c:

Go to the source code of this file.

Functions

static void usb2_phy_init (struct device *dev)
 
static void ehci_init (struct device *dev)
 

Variables

static const struct reg_script ehci_init_script []
 
static const struct reg_script ehci_clock_gating_script []
 
static const struct reg_script ehci_disable_script []
 
static const struct reg_script ehci_hc_reset []
 
static struct device_operations ehci_device_ops
 
static const struct pci_driver baytrail_ehci __pci_driver
 

Function Documentation

◆ ehci_init()

static void ehci_init ( struct device dev)
static

Definition at line 111 of file ehci.c.

◆ usb2_phy_init()

Variable Documentation

◆ __pci_driver

const struct pci_driver baytrail_ehci __pci_driver
static
Initial value:
= {
.ops = &ehci_device_ops,
.vendor = PCI_VID_INTEL,
.device = EHCI_DEVID
}
static struct device_operations ehci_device_ops
Definition: ehci.c:151
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
#define EHCI_DEVID
Definition: pci_devs.h:134

Definition at line 111 of file ehci.c.

◆ ehci_clock_gating_script

const struct reg_script ehci_clock_gating_script[]
static
Initial value:
= {
REG_PCI_OR32(0x7c, 0x00004000),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be),
}
#define RCBA_BASE_ADDRESS
Definition: iomap.h:42
#define REG_PCI_OR32(reg_, value_)
Definition: reg_script.h:187
#define REG_MMIO_WRITE32(reg_, value_)
Definition: reg_script.h:273
#define REG_SCRIPT_END
Definition: reg_script.h:427

Definition at line 1 of file ehci.c.

◆ ehci_device_ops

struct device_operations ehci_device_ops
static
Initial value:
= {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ehci_init,
.ops_pci = &soc_pci_ops,
}
static void ehci_init(struct device *dev)
Definition: ehci.c:111
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
void pci_dev_read_resources(struct device *dev)
Definition: pci_device.c:534
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691
struct pci_operations soc_pci_ops
Definition: chip.c:51

Definition at line 111 of file ehci.c.

◆ ehci_disable_script

const struct reg_script ehci_disable_script[]
static
Initial value:
= {
}
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
#define REG_RES_RMW32(bar_, reg_, mask_, value_)
Definition: reg_script.h:331
#define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_)
Definition: reg_script.h:349
#define REG_MMIO_OR32(reg_, value_)
Definition: reg_script.h:291
#define REG_PCI_RMW32(reg_, mask_, value_)
Definition: reg_script.h:175
#define USB2CMD_ASE
Definition: ehci.h:16
#define USB2CMD
Definition: ehci.h:15
#define USB2STS
Definition: ehci.h:20
#define RCBA_EHCI_DIS
Definition: ehci.h:25
#define EHCI_SBRN_FLA_PWC
Definition: ehci.h:9
#define INTRDIS
Definition: ehci.h:8
#define PORTWKCAPMASK
Definition: ehci.h:11
#define USB2CMD_PSE
Definition: ehci.h:17
#define RCBA_FUNC_DIS
Definition: ehci.h:24
#define PORTWKIMP
Definition: ehci.h:10
#define USB2STS_HCHALT
Definition: ehci.h:21
#define USB2CMD_RS
Definition: ehci.h:19
#define EHCI_CMD_STS
Definition: ehci.h:7

Definition at line 1 of file ehci.c.

◆ ehci_hc_reset

const struct reg_script ehci_hc_reset[]
static
Initial value:
= {
}
#define REG_RES_OR16(bar_, reg_, value_)
Definition: reg_script.h:341
#define USB2CMD_HCRESET
Definition: ehci.h:18

Definition at line 1 of file ehci.c.

◆ ehci_init_script

const struct reg_script ehci_init_script[]
static
Initial value:
= {
REG_PCI_OR16(0x7a, 0x14de),
REG_PCI_OR32(0x7c, 0x0000000c),
REG_PCI_OR32(0x8c, 0x00000001),
REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000),
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0),
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007),
REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003),
}
#define IOSF_PORT_USBPHY
Definition: iosf.h:99
#define REG_MMIO_RMW32(reg_, mask_, value_)
Definition: reg_script.h:279
#define REG_PCI_OR16(reg_, value_)
Definition: reg_script.h:185

Definition at line 1 of file ehci.c.