clock.h File Reference

#include <soc/addressmap.h>
#include <types.h>
#include <soc/clock_common.h>

Include dependency graph for clock.h:

Go to the source code of this file.

Data Structures
struct	sc7280_gpll
struct	sc7280_disp_cc
struct	sc7280_pcie
struct	sc7280_gcc
struct	sc7280_apss_pll
struct	sc7280_apss_clock
struct	pcie

Macros
#define	SRC_XO_HZ   (19200 * KHz)
#define	GPLL0_EVEN_HZ   (300 * MHz)
#define	GPLL0_MAIN_HZ   (600 * MHz)
#define	CLK_100MHZ   (100 * MHz)
#define	L_VAL_1516P8MHz   0x4F
#define	L_VAL_1190P4MHz   0x3E
#define	QUPV3_WRAP0_CLK_ENA_S(idx)   (10 + idx)
#define	QUPV3_WRAP1_CLK_ENA_S(idx)   (22 + idx)
#define	QUPV3_WRAP1_CLK_ENA_1_S(idx)   (7 + idx)
#define	clock_reset_aop()    clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT)
#define	clock_reset_shrm()    clock_reset_subsystem(&shrm->shrm_sproc_ctrl, SHRM_RUN_STALL)

Enumerations
enum	clk_pll_src {   SRC_XO_19_2MHZ = 0 , SRC_GPLL0_MAIN_600MHZ = 1 , SRC_GPLL0_EVEN_300MHZ = 6 , SRC_XO_19_2MHZ = 0 ,   SRC_GPLL0_MAIN_600MHZ = 1 , SRC_GPLL9_MAIN_808MHZ = 2 , SRC_GCC_DISP_GPLL0_CLK = 4 , SRC_GPLL10_MAIN_384MHZ = 5 ,   SRC_GPLL0_EVEN_300MHZ = 6 }
enum	clk_pcie_src_sel { PCIE_1_PIPE_SRC_SEL = 0 , PCIE_1_XO_SRC_SEL = 2 }
enum	apcs_branch_en_vote {   QUPV3_WRAP_0_M_AHB_CLK_ENA = 6 , QUPV3_WRAP_0_S_AHB_CLK_ENA = 7 , QUPV3_WRAP0_CORE_CLK_ENA = 8 , QUPV3_WRAP0_CORE_2X_CLK_ENA = 9 ,   QUPV3_WRAP1_CORE_2X_CLK_ENA = 18 , QUPV3_WRAP1_CORE_CLK_ENA = 19 , QUPV3_WRAP_1_M_AHB_CLK_ENA = 20 , QUPV3_WRAP_1_S_AHB_CLK_ENA = 21 ,   QUPV3_WRAP_0_M_AHB_CLK_ENA = 6 , QUPV3_WRAP_0_S_AHB_CLK_ENA = 7 , QUPV3_WRAP0_CORE_CLK_ENA = 8 , QUPV3_WRAP0_CORE_2X_CLK_ENA = 9 ,   AGGRE_NOC_PCIE_1_AXI_CLK_ENA = 11 , QUPV3_WRAP1_CORE_2X_CLK_ENA = 18 , AGGRE_NOC_PCIE_TBU_CLK_ENA = 18 , QUPV3_WRAP1_CORE_CLK_ENA = 19 ,   DDRSS_PCIE_SF_CLK_ENA = 19 , QUPV3_WRAP_1_M_AHB_CLK_ENA = 20 , QUPV3_WRAP_1_S_AHB_CLK_ENA = 21 , PCIE1_PHY_RCHNG_CLK_ENA = 23 ,   PCIE_1_SLV_Q2A_AXI_CLK_ENA = 25 , PCIE_1_SLV_AXI_CLK_ENA = 26 , PCIE_1_MSTR_AXI_CLK_ENA = 27 , PCIE_1_CFG_AHB_CLK_ENA = 28 ,   AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK_ENA = 28 , PCIE_1_AUX_CLK_ENA = 29 , PCIE_1_PIPE_CLK_ENA = 30 , NO_VOTE_BIT = -1 }
enum	clk_qup {   QUP_WRAP0_S0 , QUP_WRAP0_S1 , QUP_WRAP0_S2 , QUP_WRAP0_S3 ,   QUP_WRAP0_S4 , QUP_WRAP0_S5 , QUP_WRAP1_S0 , QUP_WRAP1_S1 ,   QUP_WRAP1_S2 , QUP_WRAP1_S3 , QUP_WRAP1_S4 , QUP_WRAP1_S5 ,   QUP_WRAP0_S0 , QUP_WRAP0_S1 , QUP_WRAP0_S2 , QUP_WRAP0_S3 ,   QUP_WRAP0_S4 , QUP_WRAP0_S5 , QUP_WRAP0_S6 , QUP_WRAP0_S7 ,   QUP_WRAP1_S0 , QUP_WRAP1_S1 , QUP_WRAP1_S2 , QUP_WRAP1_S3 ,   QUP_WRAP1_S4 , QUP_WRAP1_S5 , QUP_WRAP1_S6 , QUP_WRAP1_S7 }
enum	clk_gdsc { MDSS_CORE_GDSC , PCIE_1_GDSC , MAX_GDSC }
enum	clk_mdss {   GCC_DISP_AHB , GCC_DISP_HF_AXI , GCC_DISP_SF_AXI , GCC_EDP_CLKREF_EN ,   MDSS_CLK_PCLK0 , MDSS_CLK_MDP , MDSS_CLK_VSYNC , MDSS_CLK_BYTE0 ,   MDSS_CLK_BYTE0_INTF , MDSS_CLK_ESC0 , MDSS_CLK_AHB , MDSS_CLK_EDP_PIXEL ,   MDSS_CLK_EDP_LINK , MDSS_CLK_EDP_LINK_INTF , MDSS_CLK_EDP_AUX , MDSS_CLK_COUNT }
enum	clk_pcie {   PCIE_1_SLV_Q2A_AXI_CLK , PCIE_1_SLV_AXI_CLK , PCIE_1_MSTR_AXI_CLK , PCIE_1_CFG_AHB_CLK ,   PCIE_1_AUX_CLK , AGGRE_NOC_PCIE_TBU_CLK , AGGRE_NOC_PCIE_1_AXI_CLK , DDRSS_PCIE_SF_CLK ,   PCIE1_PHY_RCHNG_CLK , AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK , PCIE_1_PIPE_CLK , PCIE_CLKREF_EN ,   GCC_PCIE_1_PIPE_MUXR , PCIE_CLK_COUNT }
enum	subsystem_reset { AOP_RESET_SHFT = 0 , SHRM_RUN_STALL = 0 }
enum	pll_config_ctl_lo {   CTUNE_SHFT = 2 , K_I_SHFT = 4 , K_P_SHFT = 7 , PFA_MSB_SHFT = 10 ,   REF_CONT_SHFT = 28 , CTUNE_SHFT = 2 , K_I_SHFT = 4 , K_P_SHFT = 7 ,   PFA_MSB_SHFT = 10 , RES_BIT_SHFT = 14 , RON_DEGEN_MUL_SHFT = 18 , ALPHA_CAL_SHFT = 20 ,   DCO_ADDER_EN_SHFT = 22 , PLL_COUNTER_EN = 27 }
enum	pll_config_ctl_hi {   CUR_ADJ_SHFT = 0 , DMET_SHFT = 4 , RES_SHFT = 6 , CUR_TRIM_SHFT = 0 ,   FREQ_DOUBLE_SHFT = 4 , ADJ_ENABLE_SHFT = 5 , ADJ_VALUE_SHFT = 6 , KLSB_SHFT = 13 ,   RON_MODE_SHFT = 17 , CHP_REF_SHFT = 19 , CHP_STARTUP = 21 , ADC_KMSB_VAL = 23 }
enum	pll_config_ctl_u1 { FAST_LOCK_LOW_L_SHFT = 4 , DCO_BIAS_ADJ_SHFT = 26 }
enum	apss_gfmux { GFMUX_SRC_SEL_BMSK = 0x3 , APCS_SRC_EARLY = 0x2 , GFMUX_SRC_SEL_BMSK = 0x3 , APCS_SRC_EARLY = 0x2 }

Functions
	check_member (sc7280_disp_cc, pclk0_cbcr, 0x1010)
	check_member (sc7280_disp_cc, vsync_cbcr, 0x102c)
	check_member (sc7280_disp_cc, ahb_cbcr, 0x1050)
	check_member (sc7280_disp_cc, edp_aux_cbcr, 0x1060)
	check_member (sc7280_pcie, slv_q2a_axi_cbcr, 0x10)
	check_member (sc7280_pcie, mstr_axi_cbcr, 0x1c)
	check_member (sc7280_pcie, pipe_cbcr, 0x30)
	check_member (sc7280_pcie, ddrss_pcie_sf_cbcr, 0x80)
	check_member (sc7280_pcie, phy_bcr, 0x101c)
	check_member (sc7280_gcc, qusb2phy_prim_bcr, 0x12000)
	check_member (sc7280_gcc, sdcc2_apps_cbcr, 0x14004)
	check_member (sc7280_gcc, sdcc4_apps_cbcr, 0x16004)
	check_member (sc7280_gcc, qup_wrap0_bcr, 0x17000)
	check_member (sc7280_gcc, qup_wrap1_bcr, 0x18000)
	check_member (sc7280_gcc, qup_wrap1_core_cbcr, 0x23138)
	check_member (sc7280_gcc, qspi_bcr, 0x4b000)
	check_member (sc7280_gcc, usb3_phy_prim_bcr, 0x50000)
	check_member (sc7280_gcc, apcs_clk_br_en1, 0x52008)
	check_member (sc7280_gcc, apcs_pll_br_en, 0x52010)
	check_member (sc7280_gcc, usb_phy_cfg_ahb2phy_bcr, 0x6a000)
	check_member (sc7280_gcc, sdcc1_ahb_cbcr, 0x75004)
	check_member (sc7280_gcc, pcie_clkref_en, 0x8c004)
	check_member (sc7280_gcc, edp_clkref_en, 0x8c008)
	check_member (sc7280_gcc, aggre_noc_pcie_tbu_cbcr, 0x90010)
	check_member (sc7280_gcc, usb30_sec_bcr, 0x9e000)
void	clock_init (void)
void	clock_configure_qspi (uint32_t hz)
void	clock_enable_qup (int qup)
void	clock_configure_sdcc1 (uint32_t hz)
void	clock_configure_sdcc2 (uint32_t hz)
void	clock_configure_dfsr (int qup)
int	clock_enable_gdsc (enum clk_gdsc gdsc_type)
int	mdss_clock_configure (enum clk_mdss clk_type, uint32_t hz, uint32_t source, uint32_t divider, uint32_t m, uint32_t n, uint32_t d)
int	mdss_clock_enable (enum clk_mdss clk_type)
int	clock_enable_pcie (enum clk_pcie clk_type)
int	clock_configure_mux (enum clk_pcie clk_type, u32 src_type)

Variables
static struct sc7280_gcc *const	gcc = (void *)GCC_BASE
static struct sc7280_apss_clock *const	apss_silver = (void *)SILVER_PLL_BASE
static struct sc7280_apss_clock *const	apss_l3 = (void *)L3_PLL_BASE
static struct sc7280_disp_cc *const	mdss = (void *)DISP_CC_BASE
static struct aoss *const	aoss = (void *)AOSS_CC_BASE
static struct shrm *const	shrm = (void *)SHRM_SPROC_BASE

Macro Definition Documentation

CLK_100MHZ

#define CLK_100MHZ   (100 * MHz)

Definition at line 13 of file clock.h.

clock_reset_aop

#define clock_reset_aop

(

void

)

clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT)

Definition at line 399 of file clock.h.

clock_reset_shrm

#define clock_reset_shrm

(

)

clock_reset_subsystem(&shrm->shrm_sproc_ctrl, SHRM_RUN_STALL)

Definition at line 401 of file clock.h.

GPLL0_EVEN_HZ

#define GPLL0_EVEN_HZ   (300 * MHz)

Definition at line 11 of file clock.h.

GPLL0_MAIN_HZ

#define GPLL0_MAIN_HZ   (600 * MHz)

Definition at line 12 of file clock.h.

L_VAL_1190P4MHz

#define L_VAL_1190P4MHz   0x3E

Definition at line 17 of file clock.h.

L_VAL_1516P8MHz

#define L_VAL_1516P8MHz   0x4F

Definition at line 16 of file clock.h.

QUPV3_WRAP0_CLK_ENA_S

#define QUPV3_WRAP0_CLK_ENA_S

(

idx

)

(10 + idx)

Definition at line 19 of file clock.h.

QUPV3_WRAP1_CLK_ENA_1_S

#define QUPV3_WRAP1_CLK_ENA_1_S

(

idx

)

(7 + idx)

Definition at line 21 of file clock.h.

QUPV3_WRAP1_CLK_ENA_S

#define QUPV3_WRAP1_CLK_ENA_S

(

idx

)

(22 + idx)

Definition at line 20 of file clock.h.

SRC_XO_HZ

#define SRC_XO_HZ   (19200 * KHz)

Definition at line 10 of file clock.h.

Enumeration Type Documentation

apcs_branch_en_vote

enum apcs_branch_en_vote

Enumerator
QUPV3_WRAP_0_M_AHB_CLK_ENA
QUPV3_WRAP_0_S_AHB_CLK_ENA
QUPV3_WRAP0_CORE_CLK_ENA
QUPV3_WRAP0_CORE_2X_CLK_ENA
QUPV3_WRAP1_CORE_2X_CLK_ENA
QUPV3_WRAP1_CORE_CLK_ENA
QUPV3_WRAP_1_M_AHB_CLK_ENA
QUPV3_WRAP_1_S_AHB_CLK_ENA
QUPV3_WRAP_0_M_AHB_CLK_ENA
QUPV3_WRAP_0_S_AHB_CLK_ENA
QUPV3_WRAP0_CORE_CLK_ENA
QUPV3_WRAP0_CORE_2X_CLK_ENA
AGGRE_NOC_PCIE_1_AXI_CLK_ENA
QUPV3_WRAP1_CORE_2X_CLK_ENA
AGGRE_NOC_PCIE_TBU_CLK_ENA
QUPV3_WRAP1_CORE_CLK_ENA
DDRSS_PCIE_SF_CLK_ENA
QUPV3_WRAP_1_M_AHB_CLK_ENA
QUPV3_WRAP_1_S_AHB_CLK_ENA
PCIE1_PHY_RCHNG_CLK_ENA
PCIE_1_SLV_Q2A_AXI_CLK_ENA
PCIE_1_SLV_AXI_CLK_ENA
PCIE_1_MSTR_AXI_CLK_ENA
PCIE_1_CFG_AHB_CLK_ENA
AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK_ENA
PCIE_1_AUX_CLK_ENA
PCIE_1_PIPE_CLK_ENA
NO_VOTE_BIT

Definition at line 37 of file clock.h.

apss_gfmux

enum apss_gfmux

Enumerator
GFMUX_SRC_SEL_BMSK
APCS_SRC_EARLY
GFMUX_SRC_SEL_BMSK
APCS_SRC_EARLY

Definition at line 370 of file clock.h.

clk_gdsc

enum clk_gdsc

Enumerator
MDSS_CORE_GDSC
PCIE_1_GDSC
MAX_GDSC

Definition at line 294 of file clock.h.

clk_mdss

enum clk_mdss

Enumerator
GCC_DISP_AHB
GCC_DISP_HF_AXI
GCC_DISP_SF_AXI
GCC_EDP_CLKREF_EN
MDSS_CLK_PCLK0
MDSS_CLK_MDP
MDSS_CLK_VSYNC
MDSS_CLK_BYTE0
MDSS_CLK_BYTE0_INTF
MDSS_CLK_ESC0
MDSS_CLK_AHB
MDSS_CLK_EDP_PIXEL
MDSS_CLK_EDP_LINK
MDSS_CLK_EDP_LINK_INTF
MDSS_CLK_EDP_AUX
MDSS_CLK_COUNT

Definition at line 300 of file clock.h.

clk_pcie

enum clk_pcie

Enumerator
PCIE_1_SLV_Q2A_AXI_CLK
PCIE_1_SLV_AXI_CLK
PCIE_1_MSTR_AXI_CLK
PCIE_1_CFG_AHB_CLK
PCIE_1_AUX_CLK
AGGRE_NOC_PCIE_TBU_CLK
AGGRE_NOC_PCIE_1_AXI_CLK
DDRSS_PCIE_SF_CLK
PCIE1_PHY_RCHNG_CLK
AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK
PCIE_1_PIPE_CLK
PCIE_CLKREF_EN
GCC_PCIE_1_PIPE_MUXR
PCIE_CLK_COUNT

Definition at line 319 of file clock.h.

clk_pcie_src_sel

enum clk_pcie_src_sel

Enumerator
PCIE_1_PIPE_SRC_SEL
PCIE_1_XO_SRC_SEL

Definition at line 32 of file clock.h.

clk_pll_src

enum clk_pll_src

Enumerator
SRC_XO_19_2MHZ
SRC_GPLL0_MAIN_600MHZ
SRC_GPLL0_EVEN_300MHZ
SRC_XO_19_2MHZ
SRC_GPLL0_MAIN_600MHZ
SRC_GPLL9_MAIN_808MHZ
SRC_GCC_DISP_GPLL0_CLK
SRC_GPLL10_MAIN_384MHZ
SRC_GPLL0_EVEN_300MHZ

Definition at line 23 of file clock.h.

clk_qup

enum clk_qup

Enumerator
QUP_WRAP0_S0
QUP_WRAP0_S1
QUP_WRAP0_S2
QUP_WRAP0_S3
QUP_WRAP0_S4
QUP_WRAP0_S5
QUP_WRAP1_S0
QUP_WRAP1_S1
QUP_WRAP1_S2
QUP_WRAP1_S3
QUP_WRAP1_S4
QUP_WRAP1_S5
QUP_WRAP0_S0
QUP_WRAP0_S1
QUP_WRAP0_S2
QUP_WRAP0_S3
QUP_WRAP0_S4
QUP_WRAP0_S5
QUP_WRAP0_S6
QUP_WRAP0_S7
QUP_WRAP1_S0
QUP_WRAP1_S1
QUP_WRAP1_S2
QUP_WRAP1_S3
QUP_WRAP1_S4
QUP_WRAP1_S5
QUP_WRAP1_S6
QUP_WRAP1_S7

Definition at line 275 of file clock.h.

pll_config_ctl_hi

enum pll_config_ctl_hi

Enumerator
CUR_ADJ_SHFT
DMET_SHFT
RES_SHFT
CUR_TRIM_SHFT
FREQ_DOUBLE_SHFT
ADJ_ENABLE_SHFT
ADJ_VALUE_SHFT
KLSB_SHFT
RON_MODE_SHFT
CHP_REF_SHFT
CHP_STARTUP
ADC_KMSB_VAL

Definition at line 353 of file clock.h.

pll_config_ctl_lo

enum pll_config_ctl_lo

Enumerator
CTUNE_SHFT
K_I_SHFT
K_P_SHFT
PFA_MSB_SHFT
REF_CONT_SHFT
CTUNE_SHFT
K_I_SHFT
K_P_SHFT
PFA_MSB_SHFT
RES_BIT_SHFT
RON_DEGEN_MUL_SHFT
ALPHA_CAL_SHFT
DCO_ADDER_EN_SHFT
PLL_COUNTER_EN

Definition at line 341 of file clock.h.

pll_config_ctl_u1

enum pll_config_ctl_u1

Enumerator
FAST_LOCK_LOW_L_SHFT
DCO_BIAS_ADJ_SHFT

Definition at line 365 of file clock.h.

subsystem_reset

enum subsystem_reset

Enumerator
AOP_RESET_SHFT
SHRM_RUN_STALL

Definition at line 336 of file clock.h.

Function Documentation

check_member() [1/25]

check_member	(	sc7280_disp_cc	,
		ahb_cbcr	,
		0x1050
	)

check_member() [2/25]

check_member	(	sc7280_disp_cc	,
		edp_aux_cbcr	,
		0x1060
	)

check_member() [3/25]

check_member	(	sc7280_disp_cc	,
		pclk0_cbcr	,
		0x1010
	)

check_member() [4/25]

check_member	(	sc7280_disp_cc	,
		vsync_cbcr	,
		0x102c
	)

check_member() [5/25]

check_member	(	sc7280_gcc	,
		aggre_noc_pcie_tbu_cbcr	,
		0x90010
	)

check_member() [6/25]

check_member	(	sc7280_gcc	,
		apcs_clk_br_en1	,
		0x52008
	)

check_member() [7/25]

check_member	(	sc7280_gcc	,
		apcs_pll_br_en	,
		0x52010
	)

check_member() [8/25]

check_member	(	sc7280_gcc	,
		edp_clkref_en	,
		0x8c008
	)

check_member() [9/25]

check_member	(	sc7280_gcc	,
		pcie_clkref_en	,
		0x8c004
	)

check_member() [10/25]

check_member	(	sc7280_gcc	,
		qspi_bcr	,
		0x4b000
	)

check_member() [11/25]

check_member	(	sc7280_gcc	,
		qup_wrap0_bcr	,
		0x17000
	)

check_member() [12/25]

check_member	(	sc7280_gcc	,
		qup_wrap1_bcr	,
		0x18000
	)

check_member() [13/25]

check_member	(	sc7280_gcc	,
		qup_wrap1_core_cbcr	,
		0x23138
	)

check_member() [14/25]

check_member	(	sc7280_gcc	,
		qusb2phy_prim_bcr	,
		0x12000
	)

check_member() [15/25]

check_member	(	sc7280_gcc	,
		sdcc1_ahb_cbcr	,
		0x75004
	)

check_member() [16/25]

check_member	(	sc7280_gcc	,
		sdcc2_apps_cbcr	,
		0x14004
	)

check_member() [17/25]

check_member	(	sc7280_gcc	,
		sdcc4_apps_cbcr	,
		0x16004
	)

check_member() [18/25]

check_member	(	sc7280_gcc	,
		usb30_sec_bcr	,
		0x9e000
	)

check_member() [19/25]

check_member	(	sc7280_gcc	,
		usb3_phy_prim_bcr	,
		0x50000
	)

check_member() [20/25]

check_member	(	sc7280_gcc	,
		usb_phy_cfg_ahb2phy_bcr	,
		0x6a000
	)

check_member() [21/25]

check_member	(	sc7280_pcie	,
		ddrss_pcie_sf_cbcr	,
		0x80
	)

check_member() [22/25]

check_member	(	sc7280_pcie	,
		mstr_axi_cbcr	,
		0x1c
	)

check_member() [23/25]

check_member	(	sc7280_pcie	,
		phy_bcr	,
		0x101c
	)

check_member() [24/25]

check_member	(	sc7280_pcie	,
		pipe_cbcr	,
		0x30
	)

check_member() [25/25]

check_member	(	sc7280_pcie	,
		slv_q2a_axi_cbcr	,
		0x10
	)

clock_configure_dfsr()

void clock_configure_dfsr

(

int

qup

)

Definition at line 126 of file clock.c.

References ARRAY_SIZE, clock_configure_dfsr_table(), and qupv3_wrap_cfg.

Referenced by qupv3_se_fw_load_and_init().

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clock_configure_mux()

int clock_configure_mux	(	enum clk_pcie	clk_type,
		u32	src_type
	)

Definition at line 335 of file clock.c.

clock_configure_qspi()

void clock_configure_qspi

(

uint32_t

hz

)

Definition at line 117 of file clock.c.

References ARRAY_SIZE, clock_configure(), clock_enable(), gcc, and qspi_core_cfg.

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clock_configure_sdcc1()

void clock_configure_sdcc1

(

uint32_t

hz

)

Definition at line 293 of file clock.c.

References ARRAY_SIZE, alpha_pll_reg_val_config::cal_l_val, CLK_100MHZ, clock_configure(), clock_configure_enable_gpll(), clock_enable(), alpha_pll_reg_val_config::fsm_enable, gcc, alpha_pll_reg_val_config::l_val, alpha_pll_reg_val_config::reg_apcs_pll_br_en, alpha_pll_reg_val_config::reg_cal_l, alpha_pll_reg_val_config::reg_l, alpha_pll_reg_val_config::reg_mode, alpha_pll_reg_val_config::reg_opmode, and sdcc1_core_cfg.

Referenced by mainboard_init().

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clock_configure_sdcc2()

void clock_configure_sdcc2

(

uint32_t

hz

)

Definition at line 313 of file clock.c.

References alpha_pll_reg_val_config::alpha_val, ARRAY_SIZE, alpha_pll_reg_val_config::cal_l_val, CLK_100MHZ, clock_configure(), clock_configure_enable_gpll(), clock_enable(), alpha_pll_reg_val_config::fsm_enable, gcc, alpha_pll_reg_val_config::l_val, alpha_pll_reg_val_config::reg_alpha, alpha_pll_reg_val_config::reg_apcs_pll_br_en, alpha_pll_reg_val_config::reg_cal_l, alpha_pll_reg_val_config::reg_l, alpha_pll_reg_val_config::reg_mode, alpha_pll_reg_val_config::reg_opmode, and sdcc2_core_cfg.

Referenced by mainboard_init().

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clock_enable_gdsc()

int clock_enable_gdsc

(

enum clk_gdsc

gdsc_type

)

Definition at line 335 of file clock.c.

clock_enable_pcie()

int clock_enable_pcie

(

enum clk_pcie

clk_type

)

Definition at line 335 of file clock.c.

clock_enable_qup()

void clock_enable_qup

(

int

qup

)

Definition at line 132 of file clock.c.

References qupv3_clock::cbcr, clock_enable_vote(), gcc, QUP_WRAP1_S0, QUP_WRAP1_S6, QUPV3_WRAP0_CLK_ENA_S, QUPV3_WRAP1_CLK_ENA_1_S, QUPV3_WRAP1_CLK_ENA_S, and s.

Referenced by i2c_init(), qup_spi_init(), qupv3_fw_init(), and uart_init().

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clock_init()

void clock_init

(

void

)

Definition at line 539 of file clock.c.

mdss_clock_configure()

int mdss_clock_configure	(	enum clk_mdss	clk_type,
		uint32_t	hz,
		uint32_t	source,
		uint32_t	divider,
		uint32_t	m,
		uint32_t	n,
		uint32_t	d
	)

Definition at line 335 of file clock.c.

mdss_clock_enable()

int mdss_clock_enable

(

enum clk_mdss

clk_type

)

Definition at line 335 of file clock.c.

Variable Documentation

aoss

struct aoss* const aoss = (void *)AOSS_CC_BASE

static

Definition at line 396 of file clock.h.

apss_l3

struct sc7280_apss_clock* const apss_l3 = (void *)L3_PLL_BASE

static

Definition at line 377 of file clock.h.

apss_silver

struct sc7280_apss_clock* const apss_silver = (void *)SILVER_PLL_BASE

static

Definition at line 376 of file clock.h.

gcc

struct sc7280_gcc* const gcc = (void *)GCC_BASE

static

Definition at line 375 of file clock.h.

mdss

struct sc7280_disp_cc* const mdss = (void *)DISP_CC_BASE

static

Definition at line 378 of file clock.h.

shrm

struct shrm* const shrm = (void *)SHRM_SPROC_BASE

static

Definition at line 397 of file clock.h.