coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mainboard.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include "board.h"
4 #include <bootblock_common.h>
5 #include <device/device.h>
6 #include <device/mmio.h>
7 #include <soc/clock.h>
10 #include <soc/qcom_qup_se.h>
11 #include <soc/usb/usb_common.h>
12 #include <soc/usb/snps_usb_phy.h>
13 
14 static struct usb_board_data usb0_board_data = {
15  .parameter_override_x0 = 0xe6,
16  .parameter_override_x1 = 0x8b,
17  .parameter_override_x2 = 0x16,
18  .parameter_override_x3 = 0x03,
19 };
20 
21 static void setup_usb(void)
22 {
23  /* Assert EN_PP3300_HUB for those board variants that use it. */
25 
27 }
28 
29 static void configure_sdhci(void)
30 {
31  /* Program eMMC drive strength to 16/10/10 mA */
32  write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4);
33  /* Program SD card drive strength to 16/10/10 mA */
34  write32((void *)SDC2_TLMM_CFG_ADDR, 0x1FE4);
35 }
36 
37 static void qi2s_configure_gpios(void)
38 {
39  gpio_configure(GPIO_MI2S1_SCK, GPIO106_FUNC_MI2S1_SCK,
41 
42  gpio_configure(GPIO_MI2S1_WS, GPIO108_FUNC_MI2S1_WS,
44 
45  gpio_configure(GPIO_MI2S1_DATA0, GPIO107_FUNC_MI2S1_DATA0,
47 }
48 
49 static void mainboard_init(struct device *dev)
50 {
51  /* Configure clock for eMMC */
53  /* Configure clock for SD card */
56 
59 
60  /*
61  * When coreboot firmware disables serial output,
62  * we still need to load console UART QUP FW for OS.
63  */
64  if (!CONFIG(CONSOLE_SERIAL))
66 
69 
70  if (CONFIG(BOARD_GOOGLE_HEROBRINE_REV0)) {
71  /* Audio I2C */
73  /* Trackpad I2C */
75  /* SAR sensor I2C */
77  /* Fingerprint SPI */
79  } else if (CONFIG(BOARD_GOOGLE_SENOR) || CONFIG(BOARD_GOOGLE_PIGLIN)) {
80  /* APPS I2C */
82  /* ESIM SPI */
84  /* Trackpad I2C */
86  } else {
87  /* Trackpad I2C */
89  /* SAR sensor I2C */
91  /* Audio I2C */
93  /* Fingerprint SPI */
94  if (CONFIG(HEROBRINE_HAS_FINGERPRINT))
96  }
97 
98  /* Take FPMCU out of reset. Power was already applied
99  in romstage and should have stabilized by now. */
100  if (CONFIG(HEROBRINE_HAS_FINGERPRINT))
102 
103  setup_usb();
105 }
106 
107 static void mainboard_enable(struct device *dev)
108 {
109  dev->ops->init = &mainboard_init;
110 }
111 
113  .name = CONFIG_MAINBOARD_PART_NUMBER,
114  .enable_dev = mainboard_enable,
115 };
struct chip_operations mainboard_ops
Definition: mainboard.c:19
#define GPIO_OUTPUT
Definition: gpio_ftns.h:23
static void write32(void *addr, uint32_t val)
Definition: mmio.h:40
#define MHz
Definition: helpers.h:80
@ CONFIG
Definition: dsi_common.h:201
#define GPIO_FP_RST_L
Definition: board.h:48
#define GPIO_MI2S1_WS
Definition: board.h:36
#define GPIO_MI2S1_SCK
Definition: board.h:34
#define GPIO_MI2S1_DATA0
Definition: board.h:35
#define USB_HUB_LDO_EN
Definition: board.h:30
static void mainboard_init(struct device *dev)
Definition: mainboard.c:49
static void qi2s_configure_gpios(void)
Definition: mainboard.c:37
static void configure_sdhci(void)
Definition: mainboard.c:29
static struct usb_board_data usb0_board_data
Definition: mainboard.c:14
static void setup_usb(void)
Definition: mainboard.c:21
static void mainboard_enable(struct device *dev)
Definition: mainboard.c:107
void gpio_output(gpio_t gpio, int value)
Definition: gpio.c:194
@ GPIO_16MA
Definition: gpio_common.h:77
@ GPIO_NO_PULL
Definition: gpio_common.h:62
void setup_usb_host0(void *board_data)
Definition: usb.c:137
@ SE_PROTOCOL_I2C
@ SE_PROTOCOL_UART
@ SE_PROTOCOL_SPI
void gpi_firmware_load(int addr)
Definition: qupv3_config.c:184
void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol, unsigned int mode)
Definition: qupv3_config.c:13
@ QUPV3_0_SE2
Definition: qcom_qup_se.h:15
@ QUPV3_0_SE5
Definition: qcom_qup_se.h:18
@ QUPV3_1_SE4
Definition: qcom_qup_se.h:23
@ QUPV3_0_SE0
Definition: qcom_qup_se.h:13
@ QUPV3_1_SE5
Definition: qcom_qup_se.h:24
@ QUPV3_0_SE1
Definition: qcom_qup_se.h:14
@ QUPV3_1_SE3
Definition: qcom_qup_se.h:22
@ QUPV3_1_SE1
Definition: qcom_qup_se.h:20
@ QUPV3_0_SE7
Definition: qcom_qup_se.h:21
void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, uint32_t drive_str, uint32_t enable)
Definition: gpio.c:7
#define SDC1_TLMM_CFG_ADDR
Definition: addressmap.h:13
#define SDC2_TLMM_CFG_ADDR
Definition: addressmap.h:61
void clock_configure_sdcc1(uint32_t hz)
Definition: clock.c:293
void clock_configure_sdcc2(uint32_t hz)
Definition: clock.c:313
#define QUP_0_GSI_BASE
Definition: addressmap.h:44
#define QUP_1_GSI_BASE
Definition: addressmap.h:56
const char * name
Definition: device.h:29
void(* init)(struct device *dev)
Definition: device.h:42
Definition: device.h:107
struct device_operations * ops
Definition: device.h:143
u8 parameter_override_x0
Definition: snps_usb_phy.h:8