3 #include <soc/addressmap.h>
7 #ifndef __SOC_QUALCOMM_SC7280_CLOCK_H__
8 #define __SOC_QUALCOMM_SC7280_CLOCK_H__
10 #define SRC_XO_HZ (19200 * KHz)
11 #define GPLL0_EVEN_HZ (300 * MHz)
12 #define GPLL0_MAIN_HZ (600 * MHz)
13 #define CLK_100MHZ (100 * MHz)
16 #define L_VAL_1516P8MHz 0x4F
17 #define L_VAL_1190P4MHz 0x3E
19 #define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx)
20 #define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx)
21 #define QUPV3_WRAP1_CLK_ENA_1_S(idx) (7 + idx)
399 #define clock_reset_aop() \
400 clock_reset_subsystem(&aoss->aoss_cc_apcs_misc, AOP_RESET_SHFT)
401 #define clock_reset_shrm() \
402 clock_reset_subsystem(&shrm->shrm_sproc_ctrl, SHRM_RUN_STALL)
int clock_configure_qspi(uint32_t hz)
int mdss_clock_configure(enum mdss_clock clk_type, uint32_t source, uint32_t divider, uint32_t m, uint32_t n, uint32_t d)
int mdss_clock_enable(enum mdss_clock clk_type)
void clock_enable_qup(int qup)
@ QUPV3_WRAP_1_S_AHB_CLK_ENA
@ QUPV3_WRAP_1_M_AHB_CLK_ENA
@ QUPV3_WRAP_0_S_AHB_CLK_ENA
@ QUPV3_WRAP0_CORE_2X_CLK_ENA
@ QUPV3_WRAP1_CORE_2X_CLK_ENA
@ QUPV3_WRAP1_CORE_CLK_ENA
@ QUPV3_WRAP_0_M_AHB_CLK_ENA
@ QUPV3_WRAP0_CORE_CLK_ENA
check_member(sc7180_gcc, usb30_prim_bcr, 0xf000)
void clock_configure_dfsr(int qup)
static struct sc7280_gcc *const gcc
static struct sc7280_apss_clock *const apss_silver
static struct sc7280_disp_cc *const mdss
void clock_configure_sdcc1(uint32_t hz)
int clock_enable_gdsc(enum clk_gdsc gdsc_type)
int clock_enable_pcie(enum clk_pcie clk_type)
static struct sc7280_apss_clock *const apss_l3
void clock_configure_sdcc2(uint32_t hz)
@ PCIE1_PHY_RCHNG_CLK_ENA
@ AGGRE_NOC_PCIE_TBU_CLK_ENA
@ AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK_ENA
@ PCIE_1_MSTR_AXI_CLK_ENA
@ PCIE_1_SLV_Q2A_AXI_CLK_ENA
@ AGGRE_NOC_PCIE_1_AXI_CLK_ENA
int clock_configure_mux(enum clk_pcie clk_type, u32 src_type)
@ AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK
@ AGGRE_NOC_PCIE_1_AXI_CLK
struct clock_rcg mdss_ahb
u8 _res9[0x1170 - 0x10fc]
u8 _res6[0x10c0 - 0x1098]
u8 _res13[0x20000 - 0x11d8]
u8 _res5[0x1090 - 0x108c]
u8 _res2[0x102c - 0x1018]
u8 _res4[0x1078 - 0x1064]
struct clock_rcg_mnd edp_pixel
struct clock_rcg edp_link
u8 _res12[0x11d0 - 0x11a8]
u8 _res7[0x10d8 - 0x10c8]
u8 _res10[0x1188 - 0x1178]
u8 _res11[0x11a0 - 0x119c]
u8 _res8[0x10f4 - 0x10e0]
u8 _res1[0x1010 - 0x1008]
struct clock_rcg_mnd pclk0
u8 _res3[0x1050 - 0x103c]
u8 _res8[0x23000 - 0x1e044]
struct clock_rcg_mnd sdcc4
struct qupv3_clock qup_wrap1_s[8]
u8 _res19[0x75004 - 0x6a004]
u8 _res4[0x17000 - 0x16020]
u32 usb_phy_cfg_ahb2phy_bcr
u8 _res15[0x52000 - 0x5000c]
u32 qup_wrap0_core_2x_cbcr
struct clock_rcg qspi_core
u32 qup_wrap1_core_2x_cbcr
u8 _res3[0x16004 - 0x14020]
struct clock_rcg_mnd sdcc2
struct sc7280_pcie pcie_1
struct qupv3_clock qup_wrap0_s[8]
u8 _res21[0x8d000 - 0x8c00c]
struct clock_rcg qup_wrap1_core_2x
u8 _res13[0x4b000 - 0x27018]
u8 _res6[0x1c000 - 0x1898c]
u8 _res12[0x27014 - 0x27010]
u8 _res9[0x23138 - 0x23014]
u8 _res18[0x6a000 - 0x52014]
u8 _res7[0x1e000 - 0x1c044]
u8 _res23[0x9e000 - 0x90014]
u8 _res10[0x27004 - 0x2314c]
struct clock_rcg_mnd sdcc1
struct clock_rcg qup_wrap0_core_2x
u8 _res1[0x12000 - 0xf004]
u8 _res16[0x52008 - 0x52004]
u8 _res11[0x2700c - 0x27008]
struct sc7280_gpll gpll10
u32 aggre_noc_pcie_tbu_cbcr
u8 _res14[0x50000 - 0x4b014]
u8 _res17[0x52010 - 0x5200c]
u8 _res20[0x8c004 - 0x75020]
u8 _res22[0x90010 - 0x8e020]
u8 _res5[0x18000 - 0x1798c]
u8 _res24[0x1000000 - 0x90014]
u8 _res2[0x14004 - 0x12008]
u32 aggre_noc_pcie_axi_cbcr
u8 _res3[0x18d024 - 0x18d020]
u32 aggre_noc_pcie_center_sf_axi_cbcr
u8 _res8[0x18e01c - 0x18d08c]
u8 _res4[0x18d030 - 0x18d02c]
u8 _res5[0x18d038 - 0x18d034]
u8 _res2[0x18d01c - 0x18d018]
u8 _res6[0x18d054 - 0x18d03c]
u8 _res1[0x18d010 - 0x18d008]
u8 _res7[0x18d080 - 0x18d058]
#define m(clkreg, src_bits, pmcreg, dst_bits)