pch.c

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/* SPDX-License-Identifier: GPL-2.0-only */
 
#include <console/console.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include "pch.h"
 
/* Set bit in function disable register to hide this device */
static void pch_disable_devfn(struct device *dev)
{
        switch (dev->path.pci.devfn) {
        case PCI_DEVFN(22, 0): /* MEI #1 */
                RCBA32_OR(FD2, PCH_DISABLE_MEI1);
                break;
        case PCI_DEVFN(22, 1): /* MEI #2 */
                RCBA32_OR(FD2, PCH_DISABLE_MEI2);
                break;
        case PCI_DEVFN(22, 2): /* IDE-R */
                RCBA32_OR(FD2, PCH_DISABLE_IDER);
                break;
        case PCI_DEVFN(22, 3): /* KT */
                RCBA32_OR(FD2, PCH_DISABLE_KT);
                break;
        case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
                RCBA32_OR(BUC, PCH_DISABLE_GBE);
                break;
        case PCI_DEVFN(26, 0): /* EHCI #2 */
                RCBA32_OR(FD, PCH_DISABLE_EHCI2);
                break;
        case PCI_DEVFN(27, 0): /* HD Audio Controller */
                RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
                break;
        case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
        case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
        case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
        case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
        case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
        case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
        case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
        case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
                RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
                break;
        case PCI_DEVFN(29, 0): /* EHCI #1 */
                RCBA32_OR(FD, PCH_DISABLE_EHCI1);
                break;
        case PCI_DEVFN(31, 0): /* LPC */
                RCBA32_OR(FD, PCH_DISABLE_LPC);
                break;
        case PCI_DEVFN(31, 2): /* SATA #1 */
                RCBA32_OR(FD, PCH_DISABLE_SATA1);
                break;
        case PCI_DEVFN(31, 3): /* SMBUS */
                RCBA32_OR(FD, PCH_DISABLE_SMBUS);
                break;
        case PCI_DEVFN(31, 5): /* SATA #22 */
                RCBA32_OR(FD, PCH_DISABLE_SATA2);
                break;
        case PCI_DEVFN(31, 6): /* Thermal Subsystem */
                RCBA32_OR(FD, PCH_DISABLE_THERMAL);
                break;
        }
}
 
void pch_enable(struct device *dev)
{
        u16 reg16;
 
        if (!dev->enabled) {
                printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
 
                /* Ensure memory, io, and bus master are all disabled */
                reg16 = pci_read_config16(dev, PCI_COMMAND);
                reg16 &= ~(PCI_COMMAND_MASTER |
                           PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
                pci_write_config16(dev, PCI_COMMAND, reg16);
 
                /* Disable this device if possible */
                pch_disable_devfn(dev);
        } else {
                /* Enable SERR */
                pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
        }
}
 
struct chip_operations southbridge_intel_ibexpeak_ops = {
        CHIP_NAME("Intel Series 5 (Ibexpeak) Southbridge")
        .enable_dev = pch_enable,
};