coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <cf9_reset.h>
#include <device/pci_ops.h>
#include <romstage_handoff.h>
#include "sandybridge.h"
#include <arch/romstage.h>
#include <device/pci_def.h>
#include <device/device.h>
#include <northbridge/intel/sandybridge/chip.h>
#include <security/intel/txt/txt.h>
#include <security/intel/txt/txt_platform.h>
#include <security/intel/txt/txt_register.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/pmclib.h>
#include <elog.h>
Go to the source code of this file.
Functions | |
__weak void | mainboard_early_init (int s3resume) |
__weak void | mainboard_late_rcba_config (void) |
static void | configure_dpr (void) |
static void | early_pch_reset_pmcon (void) |
void | mainboard_romstage_entry (void) |
Definition at line 27 of file romstage.c.
References DPR, dpr_register::epm, HOST_BRIDGE, dpr_register::lock, pci_write_config32(), dpr_register::raw, dpr_register::size, and txt_get_chipset_dpr().
Referenced by mainboard_romstage_entry().
Definition at line 42 of file romstage.c.
References GEN_PMCON_3, PCH_LPC_DEV, and pci_and_config8().
Referenced by mainboard_romstage_entry().
Definition at line 19 of file romstage.c.
Definition at line 23 of file romstage.c.
Definition at line 49 of file romstage.c.
References BIOS_DEBUG, CONFIG, configure_dpr(), early_pch_init(), early_pch_reset_pmcon(), early_usb_init(), elog_boot_notify(), intel_txt_romstage_init(), mainboard_early_init(), mainboard_late_rcba_config(), mainboard_usb_ports, mchbar_read16(), northbridge_romstage_finalize(), perform_raminit(), post_code, printk, romstage_handoff_init(), southbridge_configure_default_intmap(), southbridge_detect_s3_resume(), southbridge_rcba_config(), SSKPD_HI, system_reset(), and systemagent_early_init().