coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
xhci.c File Reference
#include <acpi/acpi.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <reg_script.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/lpc.h>
#include <soc/pattrs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/ramstage.h>
#include <soc/xhci.h>
#include "chip.h"
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Functions

static void xhci_reset_port_usb3 (struct device *dev, int port)
 
static void xhci_route_all (struct device *dev)
 
static void xhci_init (struct device *dev)
 

Variables

struct reg_script usb3_phy_script []
 
const struct reg_script xhci_init_script []
 
const struct reg_script xhci_init_boot_script []
 
const struct reg_script xhci_init_resume_script []
 
const struct reg_script xhci_clock_gating_script []
 
static struct device_operations xhci_device_ops
 
static const struct pci_driver baytrail_xhci __pci_driver
 

Function Documentation

◆ xhci_init()

static void xhci_init ( struct device dev)
static

Definition at line 185 of file xhci.c.

◆ xhci_reset_port_usb3()

static void xhci_reset_port_usb3 ( struct device dev,
int  port 
)
static

Definition at line 137 of file xhci.c.

References reg_script::dev, PCI_BASE_ADDRESS_0, REG_RES_OR32, REG_RES_POLL32, REG_RES_RMW32, REG_SCRIPT_END, reg_script_run_on_dev(), XHCI_RESET_TIMEOUT, XHCI_USB3_PORTSC, XHCI_USB3_PORTSC_CHST, XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_WPR, and XHCI_USB3_PORTSC_WRC.

Referenced by xhci_route_all().

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◆ xhci_route_all()

Variable Documentation

◆ __pci_driver

const struct pci_driver baytrail_xhci __pci_driver
static
Initial value:
= {
.ops = &xhci_device_ops,
.vendor = PCI_VID_INTEL,
.device = XHCI_DEVID
}
#define PCI_VID_INTEL
Definition: pci_ids.h:2157
#define XHCI_DEVID
Definition: pci_devs.h:117
static struct device_operations xhci_device_ops
Definition: xhci.c:231

Definition at line 185 of file xhci.c.

◆ usb3_phy_script

struct reg_script usb3_phy_script[]
Initial value:
= {
~0x00700000, 0x00500000),
~0x001f0000, 0x000A0000),
~0x0000000f, 0x0000000b),
~0x000000f0, 0x000000f0),
~0x000001c0, 0x00000000),
~0x00000070, 0x00000020),
~0x00000002, 0x00000002),
~0x00000000, 0x00040000),
}
#define USHPHY_CDN_PLL_CONTROL
Definition: iosf.h:320
#define USHPHY_OFFSET_COR_CONFIG_DIAG
Definition: iosf.h:324
#define USHPHY_PEAKING_AMP_CONFIG_DIAG
Definition: iosf.h:323
#define IOSF_PORT_USHPHY
Definition: iosf.h:109
#define USHPHY_CCDRLF
Definition: iosf.h:322
#define USHPHY_REE_DAC_CONTROL
Definition: iosf.h:326
#define USHPHY_CDN_U1_POWER_STATE_DEF
Definition: iosf.h:327
#define USHPHY_CDN_VCO_START_CAL_POINT
Definition: iosf.h:321
#define USHPHY_VGA_GAIN_CONFIG_DIAG
Definition: iosf.h:325
#define REG_SCRIPT_END
Definition: reg_script.h:427

Definition at line 1 of file xhci.c.

◆ xhci_clock_gating_script

const struct reg_script xhci_clock_gating_script[]
Initial value:
= {
REG_PCI_RMW16(0x40, ~0x0600, 0x0100),
REG_PCI_RMW8(0x42, ~0x38, 0x04),
REG_PCI_RMW16(0x44, ~0x0030, 0x0008),
REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000),
REG_PCI_WRITE16(0xa4, 0x0000),
REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000),
REG_PCI_WRITE32(0x50, 0x0bce6e5f),
}
#define REG_PCI_RMW16(reg_, mask_, value_)
Definition: reg_script.h:173
#define REG_PCI_RMW8(reg_, mask_, value_)
Definition: reg_script.h:171
#define REG_PCI_RMW32(reg_, mask_, value_)
Definition: reg_script.h:175
#define REG_PCI_WRITE16(reg_, value_)
Definition: reg_script.h:167
#define REG_PCI_WRITE32(reg_, value_)
Definition: reg_script.h:169

Definition at line 1 of file xhci.c.

◆ xhci_device_ops

struct device_operations xhci_device_ops
static
Initial value:
= {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = xhci_init,
.ops_pci = &soc_pci_ops,
}
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
void pci_dev_read_resources(struct device *dev)
Definition: pci_device.c:534
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691
struct pci_operations soc_pci_ops
Definition: chip.c:51
static void xhci_init(struct device *dev)
Definition: xhci.c:185

Definition at line 185 of file xhci.c.

◆ xhci_init_boot_script

const struct reg_script xhci_init_boot_script[]
Initial value:
= {
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040),
REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0),
}
#define PCI_BASE_ADDRESS_0
Definition: pci_def.h:63
#define REG_RES_RMW32(bar_, reg_, mask_, value_)
Definition: reg_script.h:331
#define REG_SCRIPT_NEXT(next_)
Definition: reg_script.h:411
struct reg_script usb3_phy_script[]
Definition: xhci.c:23
const struct reg_script xhci_init_script[]
Definition: xhci.c:44

Definition at line 1 of file xhci.c.

◆ xhci_init_resume_script

const struct reg_script xhci_init_resume_script[]
Initial value:

Definition at line 1 of file xhci.c.

◆ xhci_init_script

const struct reg_script xhci_init_script[]

Definition at line 1 of file xhci.c.