clock.c File Reference

#include <assert.h>
#include <commonlib/helpers.h>
#include <device/mmio.h>
#include <soc/clock.h>
#include <types.h>

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Functions
static enum cb_err	clock_configure_gpll0 (void)
void	clock_configure_qspi (uint32_t hz)
void	clock_enable_qup (int qup)
void	clock_configure_sdcc1 (uint32_t hz)
void	clock_configure_sdcc2 (uint32_t hz)
void	clock_configure_dfsr (int qup)
static enum cb_err	pll_init_and_set (struct sc7280_apss_clock *apss, u32 l_val)
enum cb_err	clock_enable_gdsc (enum clk_gdsc gdsc_type)
enum cb_err	mdss_clock_configure (enum clk_mdss clk_type, uint32_t hz, uint32_t source, uint32_t divider, uint32_t m, uint32_t n, uint32_t d_2)
enum cb_err	mdss_clock_enable (enum clk_mdss clk_type)
enum cb_err	clock_enable_pcie (enum clk_pcie clk_type)
enum cb_err	clock_configure_mux (enum clk_pcie clk_type, u32 src_type)
static void	speed_up_boot_cpu (void)
void	clock_init (void)

Variables
static struct clock_freq_config	qspi_core_cfg []
static struct clock_freq_config	qupv3_wrap_cfg []
static struct clock_freq_config	sdcc1_core_cfg []
static struct clock_freq_config	sdcc2_core_cfg []
static struct pcie	pcie_cfg []
static struct clock_freq_config	mdss_mdp_cfg []
static struct clock_rcg *	mdss_clock [MDSS_CLK_COUNT]
static struct clock_rcg_mnd *	mdss_clock_mnd [MDSS_CLK_COUNT]
static u32 *	mdss_cbcr [MDSS_CLK_COUNT]
static u32 *	gdsc [MAX_GDSC]

Function Documentation

clock_configure_dfsr()

void clock_configure_dfsr

(

int

qup

)

Definition at line 335 of file clock.c.

References ARRAY_SIZE, clock_configure_dfsr_table(), and qupv3_wrap_cfg.

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clock_configure_gpll0()

static enum cb_err clock_configure_gpll0 ( void  )

static

Definition at line 245 of file clock.c.

References gcc, mdss, MDSS_CORE_GDSC, and PCIE_1_GDSC.

Referenced by clock_init().

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clock_configure_mux()

enum cb_err clock_configure_mux	(	enum clk_pcie	clk_type,
		u32	src_type
	)

Definition at line 335 of file clock.c.

clock_configure_qspi()

void clock_configure_qspi

(

uint32_t

hz

)

Definition at line 264 of file clock.c.

References ARRAY_SIZE, clock_configure(), clock_enable(), gcc, and qspi_core_cfg.

Referenced by quadspi_init().

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clock_configure_sdcc1()

void clock_configure_sdcc1

(

uint32_t

hz

)

Definition at line 293 of file clock.c.

References ARRAY_SIZE, alpha_pll_reg_val_config::cal_l_val, CLK_100MHZ, clock_configure(), clock_configure_enable_gpll(), clock_enable(), alpha_pll_reg_val_config::fsm_enable, gcc, alpha_pll_reg_val_config::l_val, alpha_pll_reg_val_config::reg_apcs_pll_br_en, alpha_pll_reg_val_config::reg_cal_l, alpha_pll_reg_val_config::reg_l, alpha_pll_reg_val_config::reg_mode, alpha_pll_reg_val_config::reg_opmode, and sdcc1_core_cfg.

Referenced by mainboard_init().

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clock_configure_sdcc2()

void clock_configure_sdcc2

(

uint32_t

hz

)

Definition at line 313 of file clock.c.

References alpha_pll_reg_val_config::alpha_val, ARRAY_SIZE, alpha_pll_reg_val_config::cal_l_val, CLK_100MHZ, clock_configure(), clock_configure_enable_gpll(), clock_enable(), alpha_pll_reg_val_config::fsm_enable, gcc, alpha_pll_reg_val_config::l_val, alpha_pll_reg_val_config::reg_alpha, alpha_pll_reg_val_config::reg_apcs_pll_br_en, alpha_pll_reg_val_config::reg_cal_l, alpha_pll_reg_val_config::reg_l, alpha_pll_reg_val_config::reg_mode, alpha_pll_reg_val_config::reg_opmode, and sdcc2_core_cfg.

Referenced by mainboard_init().

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clock_enable_gdsc()

enum cb_err clock_enable_gdsc

(

enum clk_gdsc

gdsc_type

)

Definition at line 335 of file clock.c.

clock_enable_pcie()

enum cb_err clock_enable_pcie

(

enum clk_pcie

clk_type

)

Definition at line 335 of file clock.c.

clock_enable_qup()

void clock_enable_qup

(

int

qup

)

Definition at line 273 of file clock.c.

References qupv3_clock::cbcr, clock_enable_vote(), gcc, QUP_WRAP1_S0, QUP_WRAP1_S6, QUPV3_WRAP0_CLK_ENA_S, QUPV3_WRAP1_CLK_ENA_1_S, QUPV3_WRAP1_CLK_ENA_S, and s.

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clock_init()

void clock_init

(

void

)

Definition at line 484 of file clock.c.

References clock_configure_gpll0(), clock_enable_vote(), gcc, QUPV3_WRAP0_CORE_2X_CLK_ENA, QUPV3_WRAP0_CORE_CLK_ENA, QUPV3_WRAP1_CORE_2X_CLK_ENA, QUPV3_WRAP1_CORE_CLK_ENA, QUPV3_WRAP_0_M_AHB_CLK_ENA, QUPV3_WRAP_0_S_AHB_CLK_ENA, QUPV3_WRAP_1_M_AHB_CLK_ENA, QUPV3_WRAP_1_S_AHB_CLK_ENA, and speed_up_boot_cpu().

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mdss_clock_configure()

enum cb_err mdss_clock_configure	(	enum clk_mdss	clk_type,
		uint32_t	hz,
		uint32_t	source,
		uint32_t	divider,
		uint32_t	m,
		uint32_t	n,
		uint32_t	d_2
	)

Definition at line 335 of file clock.c.

mdss_clock_enable()

enum cb_err mdss_clock_enable

(

enum clk_mdss

clk_type

)

Definition at line 335 of file clock.c.

pll_init_and_set()

static enum cb_err pll_init_and_set ( struct sc7280_apss_clock *  apss, u32  l_val  )

static

Definition at line 335 of file clock.c.

Referenced by speed_up_boot_cpu().

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speed_up_boot_cpu()

static void speed_up_boot_cpu ( void  )

static

Definition at line 473 of file clock.c.

References apss_l3, apss_silver, BIOS_DEBUG, L_VAL_1190P4MHz, L_VAL_1516P8MHz, pll_init_and_set(), and printk.

Referenced by clock_init().

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Variable Documentation

gdsc

u32* gdsc[MAX_GDSC]

static

Initial value:

= {
        [PCIE_1_GDSC] = &gcc->pcie_1.gdscr,
        [MDSS_CORE_GDSC] = &mdss->core_gdsc,
}

Definition at line 245 of file clock.c.

mdss_cbcr

u32* mdss_cbcr[MDSS_CLK_COUNT]

static

Initial value:

= {
        [GCC_DISP_AHB] = &gcc->disp_ahb_cbcr,
        [GCC_DISP_HF_AXI] = &gcc->disp_hf_axi_cbcr,
        [GCC_DISP_SF_AXI] = &gcc->disp_sf_axi_cbcr,
        [GCC_EDP_CLKREF_EN] = &gcc->edp_clkref_en,
        [MDSS_CLK_PCLK0] = &mdss->pclk0_cbcr,
        [MDSS_CLK_MDP] = &mdss->mdp_cbcr,
        [MDSS_CLK_VSYNC] = &mdss->vsync_cbcr,
        [MDSS_CLK_BYTE0] = &mdss->byte0_cbcr,
        [MDSS_CLK_BYTE0_INTF] = &mdss->byte0_intf_cbcr,
        [MDSS_CLK_ESC0] = &mdss->esc0_cbcr,
        [MDSS_CLK_AHB] = &mdss->ahb_cbcr,
        [MDSS_CLK_EDP_PIXEL] = &mdss->edp_pixel_cbcr,
        [MDSS_CLK_EDP_LINK] = &mdss->edp_link_cbcr,
        [MDSS_CLK_EDP_LINK_INTF] = &mdss->edp_link_intf_cbcr,
        [MDSS_CLK_EDP_AUX] = &mdss->edp_aux_cbcr,
}

Definition at line 227 of file clock.c.

mdss_clock

struct clock_rcg* mdss_clock[MDSS_CLK_COUNT]

static

Initial value:

= {
        [MDSS_CLK_MDP] = &mdss->mdp,
        [MDSS_CLK_VSYNC] = &mdss->vsync,
        [MDSS_CLK_ESC0] = &mdss->esc0,
        [MDSS_CLK_BYTE0] = &mdss->byte0,
        [MDSS_CLK_BYTE0_INTF] = &mdss->byte0,
        [MDSS_CLK_AHB] = &mdss->mdss_ahb,
        [MDSS_CLK_EDP_LINK] = &mdss->edp_link,
        [MDSS_CLK_EDP_LINK_INTF] = &mdss->edp_link,
        [MDSS_CLK_EDP_AUX] = &mdss->edp_aux,
}

Definition at line 210 of file clock.c.

mdss_clock_mnd

struct clock_rcg_mnd* mdss_clock_mnd[MDSS_CLK_COUNT]

static

Initial value:

= {
        [MDSS_CLK_PCLK0] = &mdss->pclk0,
        [MDSS_CLK_EDP_PIXEL] = &mdss->edp_pixel,
}

Definition at line 222 of file clock.c.

mdss_mdp_cfg

struct clock_freq_config mdss_mdp_cfg[]

static

Initial value:

= {
        {
                .hz = 200 * MHz,
                .src = SRC_GCC_DISP_GPLL0_CLK,
                .div = QCOM_CLOCK_DIV(3),
        },
        {
                .hz = 300 * MHz,
                .src = SRC_GCC_DISP_GPLL0_CLK,
                .div = QCOM_CLOCK_DIV(2),
        },
        {
                .hz = 400 * MHz,
                .src = SRC_GCC_DISP_GPLL0_CLK,
                .div = QCOM_CLOCK_DIV(1.5),
        },
}

Definition at line 1 of file clock.c.

pcie_cfg

struct pcie pcie_cfg[]

static

Definition at line 1 of file clock.c.

qspi_core_cfg

struct clock_freq_config qspi_core_cfg[]

static

Initial value:

= {
        {
                .hz = SRC_XO_HZ,        
                .src = SRC_XO_19_2MHZ,
                .div = QCOM_CLOCK_DIV(1),
        },
        {
                .hz = 100 * MHz,
                .src = SRC_GPLL0_MAIN_600MHZ,
                .div = QCOM_CLOCK_DIV(6),
        },
        {
                .hz = 150 * MHz,
                .src = SRC_GPLL0_MAIN_600MHZ,
                .div = QCOM_CLOCK_DIV(4),
        },
        {
                .hz = 200 * MHz,
                .src = SRC_GPLL0_MAIN_600MHZ,
                .div = QCOM_CLOCK_DIV(3),
        },
        {
                .hz = 400 * MHz,
                .src = SRC_GPLL0_MAIN_600MHZ,
                .div = QCOM_CLOCK_DIV(1.5),
        },
}

Definition at line 1 of file clock.c.

Referenced by clock_configure_qspi().

qupv3_wrap_cfg

struct clock_freq_config qupv3_wrap_cfg[]

static

Definition at line 1 of file clock.c.

Referenced by clock_configure_dfsr().

sdcc1_core_cfg

struct clock_freq_config sdcc1_core_cfg[]

static

Initial value:

= {
        {
                .hz = 100 * MHz,
                .src = SRC_GPLL0_EVEN_300MHZ,
                .div = QCOM_CLOCK_DIV(3),
        },
        {
                .hz = 192 * MHz,
                .src = SRC_GPLL10_MAIN_384MHZ,
                .div = QCOM_CLOCK_DIV(2),
        },
        {
                .hz = 384 * MHz,
                .src = SRC_GPLL10_MAIN_384MHZ,
                .div = QCOM_CLOCK_DIV(1),
        },
}

Definition at line 1 of file clock.c.

Referenced by clock_configure_sdcc1().

sdcc2_core_cfg

struct clock_freq_config sdcc2_core_cfg[]

static

Initial value:

= {
        {
                .hz = 50 * MHz,
                .src = SRC_GPLL0_EVEN_300MHZ,
                .div = QCOM_CLOCK_DIV(6),
        },
        {
                .hz = 202 * MHz,
                .src = SRC_GPLL9_MAIN_808MHZ,
                .div = QCOM_CLOCK_DIV(4),
        },
}

Definition at line 1 of file clock.c.

Referenced by clock_configure_sdcc2().