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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/mmio.h>
#include <device/pci_ops.h>
#include <cf9_reset.h>
#include <ip_checksum.h>
#include <device/pci_def.h>
#include <device/smbus_host.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/rcba.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h"
#include "chip.h"
Go to the source code of this file.
Macros | |
#define | SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) |
Functions | |
static void | wait_iobp (void) |
static u32 | read_iobp (u32 address) |
static void | write_iobp (u32 address, u32 val) |
void | early_pch_init_native_dmi_pre (void) |
void | early_pch_init_native_dmi_post (void) |
void | early_pch_init_native (void) |
static void | pch_enable_bars (void) |
static void | pch_generic_setup (void) |
static void | pch_enable_gbe (void) |
static void | pch_enable_lpc_decode (void) |
__weak void | mainboard_pch_lpc_setup (void) |
void | early_pch_init (void) |
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) |
Definition at line 19 of file early_pch.c.
Definition at line 299 of file early_pch.c.
References enable_smbus(), ENV_ROMSTAGE, mainboard_gpio_map, mainboard_pch_lpc_setup(), pch_enable_bars(), pch_enable_gbe(), pch_enable_lpc_decode(), pch_generic_setup(), and setup_pch_gpios().
Referenced by bootblock_early_southbridge_init(), and mainboard_romstage_entry().
Definition at line 136 of file early_pch.c.
References CIR1, CIR6, DMC2, pci_read_config8(), pci_write_config8(), RCBA32, RCBA8, REC, RPC, SATA_IOBP_SP0G3IR, SATA_IOBP_SP1G3IR, SOUTHBRIDGE, and write_iobp().
Referenced by init_dram_ddr3().
Definition at line 56 of file early_pch.c.
References DLCTL2, LCAP, RCBA32, and RCBA8.
Referenced by early_init_dmi().
Definition at line 295 of file early_pch.c.
Referenced by early_pch_init().
Definition at line 219 of file early_pch.c.
References ACPI_CNTL, ACPI_EN, DEFAULT_GPIOBASE, DEFAULT_PMBASE, GPIO_BASE, GPIO_CNTL, PCH_LPC_DEV, pci_write_config32(), pci_write_config8(), PMBASE, and RCBA.
Referenced by early_pch_init().
Definition at line 239 of file early_pch.c.
References BUC, device::enabled, ENV_BOOTBLOCK, full_reset(), PCH_DISABLE_GBE, pcidev_on_root(), and RCBA8.
Referenced by early_pch_init().
Definition at line 263 of file early_pch.c.
References device::chip_info, CNF1_LPC_EN, CNF2_LPC_EN, COMA_LPC_EN, COMB_LPC_EN, config, FDD_LPC_EN, KBC_LPC_EN, LPC_EN, LPC_GEN1_DEC, LPC_GEN2_DEC, LPC_GEN3_DEC, LPC_GEN4_DEC, LPC_IO_DEC, LPT_LPC_EN, MC_LPC_EN, NULL, PCH_LPC_DEV, pci_write_config16(), pci_write_config32(), and pcidev_on_root().
Referenced by early_pch_init().
Definition at line 233 of file early_pch.c.
References GCS, RCBA32, TCO1_CNT, and write_pmbase16().
Referenced by early_pch_init().
Definition at line 27 of file early_pch.c.
References address, IOBPD, IOBPIRI, IOBPS, RCBA16, RCBA32, RCBA8, and wait_iobp().
Referenced by write_iobp().
Definition at line 21 of file early_pch.c.
Referenced by read_iobp(), and write_iobp().
Definition at line 40 of file early_pch.c.
References address, IOBPD, IOBPS, RCBA16, RCBA32, RCBA8, read_iobp(), val, and wait_iobp().
Referenced by early_pch_init_native().