coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
mainboard.c File Reference
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Macros

#define SPD_SIZE   128
 
#define PM_RTC_CONTROL   0x56
 
#define PM_S_STATE_CONTROL   0xBA
 
#define SIO_PORT   0x2e
 

Functions

static void pirq_setup (void)
 
static void config_gpio_mux (void)
 
static void mainboard_enable (struct device *dev)
 
static void mainboard_final (void *chip_info)
 
const char * smbios_mainboard_serial_number (void)
 
const char * smbios_system_sku (void)
 

Variables

static const u8 mainboard_picr_data [FCH_INT_TABLE_SIZE]
 
static const u8 mainboard_intr_data [FCH_INT_TABLE_SIZE]
 
static const struct pirq_struct mainboard_pirq_data []
 
struct chip_operations mainboard_ops
 

Macro Definition Documentation

◆ PM_RTC_CONTROL

#define PM_RTC_CONTROL   0x56

Definition at line 23 of file mainboard.c.

◆ PM_S_STATE_CONTROL

#define PM_S_STATE_CONTROL   0xBA

Definition at line 24 of file mainboard.c.

◆ SIO_PORT

#define SIO_PORT   0x2e

Definition at line 125 of file mainboard.c.

◆ SPD_SIZE

#define SPD_SIZE   128

Definition at line 22 of file mainboard.c.

Function Documentation

◆ config_gpio_mux()

static void config_gpio_mux ( void  )
static

Definition at line 127 of file mainboard.c.

References CONFIG, dev_find_slot_pnp(), device::enabled, NCT5104D_GPIO0, NCT5104D_GPIO1, NCT5104D_SP3, NCT5104D_SP4, and SIO_PORT.

Referenced by mainboard_enable().

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◆ mainboard_enable()

static void mainboard_enable ( struct device dev)
static

Definition at line 226 of file mainboard.c.

References BIOS_INFO, config_gpio_mux(), mainboard_smbios_data(), device::ops, pirq_setup(), pm_read16(), PM_RTC_CONTROL, PM_S_STATE_CONTROL, pm_write16(), and printk.

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◆ mainboard_final()

static void mainboard_final ( void chip_info)
static

Definition at line 250 of file mainboard.c.

References GPIO_58, GPIO_59, and gpio_set().

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◆ pirq_setup()

static void pirq_setup ( void  )
static

Definition at line 114 of file mainboard.c.

References ARRAY_SIZE, intr_data_ptr, mainboard_intr_data, mainboard_picr_data, mainboard_pirq_data, picr_data_ptr, pirq_data_ptr, and pirq_data_size.

Referenced by mainboard_enable().

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◆ smbios_mainboard_serial_number()

const char* smbios_mainboard_serial_number ( void  )

Definition at line 263 of file mainboard.c.

References device::link_list, PCI_BASE_ADDRESS_0, PCI_DEVFN, pci_read_config32(), pcidev_on_root(), pcidev_path_behind(), read8(), serial, and snprintf().

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◆ smbios_system_sku()

const char* smbios_system_sku ( void  )

Definition at line 300 of file mainboard.c.

Variable Documentation

◆ mainboard_intr_data

const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE]
static
Initial value:
= {
[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
[0x00] = 0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F,
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
[0x10] = 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x10,
[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x30] = 0x12,0x1F,0x12,0x1F,0x12,0x1F,0x1F,0x00,
[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x40] = 0x1F,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x60] = 0x00,0x00,0x1F
}
#define FCH_INT_TABLE_SIZE

Definition at line 60 of file mainboard.c.

Referenced by pirq_setup().

◆ mainboard_ops

struct chip_operations mainboard_ops
Initial value:
= {
.enable_dev = mainboard_enable,
.final = mainboard_final,
}
static void mainboard_final(void *chip_info)
Definition: mainboard.c:250
static void mainboard_enable(struct device *dev)
Definition: mainboard.c:226

Definition at line 300 of file mainboard.c.

◆ mainboard_picr_data

const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE]
static
Initial value:
= {
[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
[0x00] = 0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
[0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x30] = 0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F,
[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x50] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
[0x60] = 0x00,0x00,0x1F
}

Definition at line 37 of file mainboard.c.

Referenced by pirq_setup().

◆ mainboard_pirq_data

const struct pirq_struct mainboard_pirq_data[]
static
Initial value:
= {
}
@ PIRQ_A
Definition: acpi_pirq_gen.h:22
@ PIRQ_C
Definition: acpi_pirq_gen.h:24
@ PIRQ_D
Definition: acpi_pirq_gen.h:25
@ PIRQ_B
Definition: acpi_pirq_gen.h:23
#define SD_DEVFN
Definition: variants.h:11
#define NB_PCIE_PORT2_DEVFN
Definition: pci_devs.h:34
#define NB_PCIE_PORT3_DEVFN
Definition: pci_devs.h:35
#define NB_PCIE_PORT1_DEVFN
Definition: pci_devs.h:33
#define GFX_DEVFN
Definition: pci_devs.h:13
#define ACTL_DEVFN
Definition: pci_devs.h:27
#define PIRQ_SATA
#define PIRQ_SMBUS
#define PIRQ_SD
#define PIRQ_NC
#define SMBUS_DEVFN
Definition: pci_devs.h:117
#define SATA_DEVFN
Definition: pci_devs.h:83
#define PIRQ_HDA
#define EHCI1_DEVFN
Definition: pci_devs.h:170
#define XHCI_DEVFN
Definition: pci_devs.h:153
#define PIRQ_OHCI2
#define PIRQ_OHCI1
#define PIRQ_EHCI3
#define PIRQ_OHCI3
#define PIRQ_EHCI2
#define PIRQ_EHCI1
#define HDA_DEVFN
Definition: pci_devs.h:69
#define OHCI1_DEVFN
Definition: pci_devs.h:34
#define EHCI3_DEVFN
Definition: pci_devs.h:49
#define OHCI3_DEVFN
Definition: pci_devs.h:36
#define EHCI2_DEVFN
Definition: pci_devs.h:48
#define OHCI2_DEVFN
Definition: pci_devs.h:35

Definition at line 60 of file mainboard.c.

Referenced by pirq_setup().