coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
report_platform.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/cpu.h>
4 #include <console/console.h>
5 #include <cpu/intel/cpu_ids.h>
6 #include <cpu/intel/microcode.h>
7 #include <cpu/x86/msr.h>
8 #include <cpu/x86/name.h>
9 #include <device/pci.h>
10 #include <device/pci_ids.h>
11 #include <device/pci_ops.h>
12 #include <soc/bootblock.h>
13 #include <soc/pch.h>
14 #include <soc/pci_devs.h>
15 
16 static struct {
18  const char *name;
19 } cpu_table[] = {
20  { CPUID_ELKHARTLAKE_A0, "Elkhartlake A0" },
21  { CPUID_ELKHARTLAKE_B0, "Elkhartlake B0/B1" },
22 };
23 
24 static struct {
26  const char *name;
27 } mch_table[] = {
28  { PCI_DID_INTEL_EHL_ID_0, "Elkhartlake SKU-0" },
29  { PCI_DID_INTEL_EHL_ID_1, "Elkhartlake SKU-1" },
30  { PCI_DID_INTEL_EHL_ID_1A, "Elkhartlake SKU-1A" },
31  { PCI_DID_INTEL_EHL_ID_2, "Elkhartlake SKU-2" },
32  { PCI_DID_INTEL_EHL_ID_2_1, "Elkhartlake SKU-2" },
33  { PCI_DID_INTEL_EHL_ID_3, "Elkhartlake SKU-3" },
34  { PCI_DID_INTEL_EHL_ID_3A, "Elkhartlake SKU-3A" },
35  { PCI_DID_INTEL_EHL_ID_4, "Elkhartlake SKU-4" },
36  { PCI_DID_INTEL_EHL_ID_5, "Elkhartlake SKU-5" },
37  { PCI_DID_INTEL_EHL_ID_6, "Elkhartlake SKU-6" },
38  { PCI_DID_INTEL_EHL_ID_7, "Elkhartlake SKU-7" },
39  { PCI_DID_INTEL_EHL_ID_8, "Elkhartlake SKU-8" },
40  { PCI_DID_INTEL_EHL_ID_9, "Elkhartlake SKU-9" },
41  { PCI_DID_INTEL_EHL_ID_10, "Elkhartlake SKU-10" },
42  { PCI_DID_INTEL_EHL_ID_11, "Elkhartlake SKU-11" },
43  { PCI_DID_INTEL_EHL_ID_12, "Elkhartlake SKU-12" },
44  { PCI_DID_INTEL_EHL_ID_13, "Elkhartlake SKU-13" },
45  { PCI_DID_INTEL_EHL_ID_14, "Elkhartlake SKU-14" },
46  { PCI_DID_INTEL_EHL_ID_15, "Elkhartlake SKU-15" },
47 };
48 
49 static struct {
51  const char *name;
52 } pch_table[] = {
53  { PCI_DID_INTEL_MCC_ESPI_0, "Elkhartlake-0" },
54  { PCI_DID_INTEL_MCC_ESPI_1, "Elkhartlake-1" },
55  { PCI_DID_INTEL_MCC_BASE_ESPI, "Elkhartlake Base" },
56  { PCI_DID_INTEL_MCC_PREMIUM_ESPI, "Elkhartlake Premium" },
57  { PCI_DID_INTEL_MCC_SUPER_ESPI, "Elkhartlake Super" },
58 };
59 
60 static struct {
62  const char *name;
63 } igd_table[] = {
64  { PCI_DID_INTEL_EHL_GT1_1, "Elkhartlake GT1-1" },
65  { PCI_DID_INTEL_EHL_GT2_1, "Elkhartlake GT2-1" },
66  { PCI_DID_INTEL_EHL_GT1_2, "Elkhartlake GT1-2" },
67  { PCI_DID_INTEL_EHL_GT1_2_1, "Elkhartlake GT1-2-1" },
68  { PCI_DID_INTEL_EHL_GT2_2, "Elkhartlake GT2-2" },
69  { PCI_DID_INTEL_EHL_GT1_3, "Elkhartlake GT1-3" },
70  { PCI_DID_INTEL_EHL_GT2_3, "Elkhartlake GT2-3" },
71 };
72 
74 {
75  return pci_read_config8(dev, PCI_REVISION_ID);
76 }
77 
78 static inline uint16_t get_dev_id(pci_devfn_t dev)
79 {
80  return pci_read_config16(dev, PCI_DEVICE_ID);
81 }
82 
83 static void report_cpu_info(void)
84 {
85  uint32_t i, cpu_id, cpu_feature_flag;
86  char cpu_name[49];
87  int vt, txt, aes;
88  static const char *const mode[] = {"NOT ", ""};
89  const char *cpu_type = "Unknown";
90 
91  fill_processor_name(cpu_name);
93 
94  /* Look for string to match the name */
95  for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
96  if (cpu_table[i].cpuid == cpu_id) {
97  cpu_type = cpu_table[i].name;
98  break;
99  }
100  }
101 
102  printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
103  printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
105 
106  cpu_feature_flag = cpu_get_feature_flags_ecx();
107  aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
108  txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
109  vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
111  "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
112  mode[aes], mode[txt], mode[vt]);
113 }
114 
115 static void report_mch_info(void)
116 {
117  int i;
118  pci_devfn_t dev = SA_DEV_ROOT;
119  uint16_t mchid = get_dev_id(dev);
120  uint8_t mch_revision = get_dev_revision(dev);
121  const char *mch_type = "Unknown";
122 
123  for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
124  if (mch_table[i].mchid == mchid) {
125  mch_type = mch_table[i].name;
126  break;
127  }
128  }
129 
130  printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
131  mchid, mch_revision, mch_type);
132 }
133 
134 static void report_pch_info(void)
135 {
136  int i;
138  uint16_t espiid = get_dev_id(dev);
139  const char *pch_type = "Unknown";
140 
141  for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
142  if (pch_table[i].espiid == espiid) {
143  pch_type = pch_table[i].name;
144  break;
145  }
146  }
147  printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
149 }
150 
151 static void report_igd_info(void)
152 {
153  int i;
154  pci_devfn_t dev = SA_DEV_IGD;
155  uint16_t igdid = get_dev_id(dev);
156  const char *igd_type = "Unknown";
157 
158  for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
159  if (igd_table[i].igdid == igdid) {
160  igd_type = igd_table[i].name;
161  break;
162  }
163  }
164  printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
165  igdid, get_dev_revision(dev), igd_type);
166 }
167 
169 {
170  report_cpu_info();
171  report_mch_info();
172  report_pch_info();
173  report_igd_info();
174 }
cpu_type
Definition: cpu.h:347
#define ARRAY_SIZE(a)
Definition: helpers.h:12
#define printk(level,...)
Definition: stdlib.h:16
uint32_t cpu_get_feature_flags_ecx(void)
Definition: cpu_common.c:72
uint32_t cpu_get_cpuid(void)
Definition: cpu_common.c:63
#define CPUID_ELKHARTLAKE_A0
Definition: cpu_ids.h:51
#define CPUID_ELKHARTLAKE_B0
Definition: cpu_ids.h:52
#define CPUID_AES
Definition: msr.h:28
#define CPUID_VMX
Definition: msr.h:24
#define CPUID_SMX
Definition: msr.h:25
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
Definition: pci_ops.h:52
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
Definition: pci_ops.h:46
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
uint32_t get_current_microcode_rev(void)
Definition: microcode.c:112
void fill_processor_name(char *processor_name)
Definition: name.c:8
void report_platform_info(void)
#define PCI_DEVICE_ID
Definition: pci_def.h:9
#define PCI_REVISION_ID
Definition: pci_def.h:41
#define PCI_DID_INTEL_MCC_SUPER_ESPI
Definition: pci_ids.h:2974
#define PCI_DID_INTEL_EHL_ID_3
Definition: pci_ids.h:4029
#define PCI_DID_INTEL_MCC_PREMIUM_ESPI
Definition: pci_ids.h:2973
#define PCI_DID_INTEL_EHL_ID_10
Definition: pci_ids.h:4037
#define PCI_DID_INTEL_EHL_ID_3A
Definition: pci_ids.h:4030
#define PCI_DID_INTEL_EHL_GT1_2
Definition: pci_ids.h:3921
#define PCI_DID_INTEL_EHL_ID_4
Definition: pci_ids.h:4031
#define PCI_DID_INTEL_MCC_ESPI_1
Definition: pci_ids.h:2971
#define PCI_DID_INTEL_MCC_ESPI_0
Definition: pci_ids.h:2970
#define PCI_DID_INTEL_EHL_ID_11
Definition: pci_ids.h:4038
#define PCI_DID_INTEL_EHL_GT2_1
Definition: pci_ids.h:3920
#define PCI_DID_INTEL_EHL_ID_14
Definition: pci_ids.h:4041
#define PCI_DID_INTEL_EHL_ID_5
Definition: pci_ids.h:4032
#define PCI_DID_INTEL_EHL_ID_1A
Definition: pci_ids.h:4026
#define PCI_DID_INTEL_EHL_ID_9
Definition: pci_ids.h:4036
#define PCI_DID_INTEL_MCC_BASE_ESPI
Definition: pci_ids.h:2972
#define PCI_DID_INTEL_EHL_ID_2
Definition: pci_ids.h:4027
#define PCI_DID_INTEL_EHL_ID_12
Definition: pci_ids.h:4039
#define PCI_DID_INTEL_EHL_ID_0
Definition: pci_ids.h:4024
#define PCI_DID_INTEL_EHL_ID_8
Definition: pci_ids.h:4035
#define PCI_DID_INTEL_EHL_ID_7
Definition: pci_ids.h:4034
#define PCI_DID_INTEL_EHL_ID_6
Definition: pci_ids.h:4033
#define PCI_DID_INTEL_EHL_GT1_2_1
Definition: pci_ids.h:3922
#define PCI_DID_INTEL_EHL_ID_15
Definition: pci_ids.h:4042
#define PCI_DID_INTEL_EHL_GT2_3
Definition: pci_ids.h:3925
#define PCI_DID_INTEL_EHL_GT2_2
Definition: pci_ids.h:3923
#define PCI_DID_INTEL_EHL_GT1_3
Definition: pci_ids.h:3924
#define PCI_DID_INTEL_EHL_ID_13
Definition: pci_ids.h:4040
#define PCI_DID_INTEL_EHL_GT1_1
Definition: pci_ids.h:3919
#define PCI_DID_INTEL_EHL_ID_2_1
Definition: pci_ids.h:4028
#define PCI_DID_INTEL_EHL_ID_1
Definition: pci_ids.h:4025
u32 pci_devfn_t
Definition: pci_type.h:8
u16 mchid
u16 igdid
const char * name
u32 cpuid
u16 espiid
unsigned int cpu_id
Definition: chip.h:47
#define PCH_DEV_ESPI
Definition: pci_devs.h:223
#define SA_DEV_IGD
Definition: pci_devs.h:33
u16 pch_type(void)
Definition: pch.c:20
#define SA_DEV_ROOT
Definition: pci_devs.h:26
static void report_igd_info(void)
static void report_mch_info(void)
static uint16_t get_dev_id(pci_devfn_t dev)
static void report_pch_info(void)
static struct @555 pch_table[]
static struct @554 mch_table[]
static struct @556 igd_table[]
static struct @553 cpu_table[]
static void report_cpu_info(void)
static uint8_t get_dev_revision(pci_devfn_t dev)
unsigned short uint16_t
Definition: stdint.h:11
unsigned int uint32_t
Definition: stdint.h:14
uint16_t u16
Definition: stdint.h:48
unsigned char uint8_t
Definition: stdint.h:8