12 #include <soc/bootblock.h>
14 #include <soc/pci_devs.h>
88 static const char *
const mode[] = {
"NOT ",
""};
107 aes = (cpu_feature_flag &
CPUID_AES) ? 1 : 0;
108 txt = (cpu_feature_flag &
CPUID_SMX) ? 1 : 0;
109 vt = (cpu_feature_flag &
CPUID_VMX) ? 1 : 0;
111 "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
112 mode[aes], mode[txt], mode[vt]);
121 const char *mch_type =
"Unknown";
131 mchid, mch_revision, mch_type);
156 const char *igd_type =
"Unknown";
#define printk(level,...)
uint32_t cpu_get_feature_flags_ecx(void)
uint32_t cpu_get_cpuid(void)
#define CPUID_ELKHARTLAKE_A0
#define CPUID_ELKHARTLAKE_B0
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
uint32_t get_current_microcode_rev(void)
void fill_processor_name(char *processor_name)
#define PCI_DID_INTEL_MCC_SUPER_ESPI
#define PCI_DID_INTEL_EHL_ID_3
#define PCI_DID_INTEL_MCC_PREMIUM_ESPI
#define PCI_DID_INTEL_EHL_ID_10
#define PCI_DID_INTEL_EHL_ID_3A
#define PCI_DID_INTEL_EHL_GT1_2
#define PCI_DID_INTEL_EHL_ID_4
#define PCI_DID_INTEL_MCC_ESPI_1
#define PCI_DID_INTEL_MCC_ESPI_0
#define PCI_DID_INTEL_EHL_ID_11
#define PCI_DID_INTEL_EHL_GT2_1
#define PCI_DID_INTEL_EHL_ID_14
#define PCI_DID_INTEL_EHL_ID_5
#define PCI_DID_INTEL_EHL_ID_1A
#define PCI_DID_INTEL_EHL_ID_9
#define PCI_DID_INTEL_MCC_BASE_ESPI
#define PCI_DID_INTEL_EHL_ID_2
#define PCI_DID_INTEL_EHL_ID_12
#define PCI_DID_INTEL_EHL_ID_0
#define PCI_DID_INTEL_EHL_ID_8
#define PCI_DID_INTEL_EHL_ID_7
#define PCI_DID_INTEL_EHL_ID_6
#define PCI_DID_INTEL_EHL_GT1_2_1
#define PCI_DID_INTEL_EHL_ID_15
#define PCI_DID_INTEL_EHL_GT2_3
#define PCI_DID_INTEL_EHL_GT2_2
#define PCI_DID_INTEL_EHL_GT1_3
#define PCI_DID_INTEL_EHL_ID_13
#define PCI_DID_INTEL_EHL_GT1_1
#define PCI_DID_INTEL_EHL_ID_2_1
#define PCI_DID_INTEL_EHL_ID_1