coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <console/console.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/pmutil.h>
#include "i82801jx.h"
#include "chip.h"
Go to the source code of this file.
Macros | |
#define | TCO_BASE 0x60 |
Functions | |
void | i82801jx_lpc_setup (void) |
void | i82801jx_setup_bars (void) |
void | i82801jx_early_init (void) |
#define TCO_BASE 0x60 |
Definition at line 66 of file early_init.c.
Definition at line 68 of file early_init.c.
References BIOS_DEBUG, enable_smbus(), ENV_ROMSTAGE, GCS, i82801jx_setup_bars(), mainboard_gpio_map, OIC, PCI_DEV, pci_read_config8(), pci_write_config8(), printk, RCBA32, RCBA8, setup_pch_gpios(), TCO_BASE, and write_pmbase16().
Referenced by mainboard_romstage_entry().
Definition at line 12 of file early_init.c.
References device::chip_info, CNF1_LPC_EN, CNF2_LPC_EN, COMA_LPC_EN, COMB_LPC_EN, config, D31F0_GEN1_DEC, D31F0_GEN2_DEC, D31F0_GEN3_DEC, D31F0_GEN4_DEC, D31F0_LPC_EN, D31F0_LPC_IODEC, D31F0_SERIRQ_CNTL, FDD_LPC_EN, GAMEH_LPC_EN, GAMEL_LPC_EN, KBC_LPC_EN, LPT_LPC_EN, MC_LPC_EN, PCI_DEV, pci_write_config16(), pci_write_config32(), pci_write_config8(), and pcidev_on_root().
Referenced by bootblock_early_southbridge_init().
Definition at line 48 of file early_init.c.
References D31F0_ACPI_CNTL, D31F0_GPIO_BASE, D31F0_GPIO_CNTL, D31F0_PMBASE, DEFAULT_GPIOBASE, DEFAULT_PMBASE, PCI_DEV, pci_or_config8(), pci_write_config32(), pci_write_config8(), and RCBA.
Referenced by bootblock_early_southbridge_init(), and i82801jx_early_init().