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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <commonlib/helpers.h>
#include <console/console.h>
#include <acpi/acpi.h>
#include <delay.h>
#include <cpu/intel/haswell/haswell.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <boot/tables.h>
#include <security/intel/txt/txt_register.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <types.h>
#include "chip.h"
#include "haswell.h"
Go to the source code of this file.
Data Structures | |
struct | fixed_mmio_descriptor |
struct | map_entry |
Macros | |
#define | MAP_ENTRY(reg_, is_64_, is_limit_, desc_) |
#define | MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) |
#define | MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) |
#define | MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) |
Enumerations | |
enum | { TOM_REG , TOUUD_REG , MESEG_BASE_REG , MESEG_LIMIT_REG , REMAP_BASE_REG , REMAP_LIMIT_REG , TOLUD_REG , BGSM_REG , BDSM_REG , TSEG_REG , NUM_MAP_ENTRIES } |
Functions | |
static const char * | northbridge_acpi_name (const struct device *dev) |
static int | get_bar (struct device *dev, unsigned int index, u32 *base, u32 *len) |
static int | get_bar_in_mchbar (struct device *dev, unsigned int index, u32 *base, u32 *len) |
static void | mc_add_fixed_mmio_resources (struct device *dev) |
static void | read_map_entry (struct device *dev, struct map_entry *entry, uint64_t *result) |
static void | mc_read_map_entries (struct device *dev, uint64_t *values) |
static void | mc_report_map_entries (struct device *dev, uint64_t *values) |
static void | mc_add_dram_resources (struct device *dev, int *resource_cnt) |
static void | mc_read_resources (struct device *dev) |
static void | disable_devices (void) |
static void | init_egress (void) |
static void | northbridge_dmi_init (void) |
static void | northbridge_topology_init (void) |
static void | northbridge_init (struct device *dev) |
static void | northbridge_final (struct device *dev) |
static void | enable_dev (struct device *dev) |
Variables | |
static struct device_operations | pci_domain_ops |
struct fixed_mmio_descriptor | mc_fixed_resources [] |
static struct map_entry | memory_map [NUM_MAP_ENTRIES] |
static struct device_operations | mc_ops |
static const unsigned short | mc_pci_device_ids [] |
static const struct pci_driver mc_driver_hsw | __pci_driver |
static struct device_operations | cpu_bus_ops |
struct chip_operations | northbridge_intel_haswell_ops |
#define MAP_ENTRY | ( | reg_, | |
is_64_, | |||
is_limit_, | |||
desc_ | |||
) |
Definition at line 179 of file northbridge.c.
#define MAP_ENTRY_BASE_32 | ( | reg_, | |
desc_ | |||
) | MAP_ENTRY(reg_, 0, 0, desc_) |
Definition at line 187 of file northbridge.c.
#define MAP_ENTRY_BASE_64 | ( | reg_, | |
desc_ | |||
) | MAP_ENTRY(reg_, 1, 0, desc_) |
Definition at line 188 of file northbridge.c.
#define MAP_ENTRY_LIMIT_64 | ( | reg_, | |
desc_ | |||
) | MAP_ENTRY(reg_, 1, 1, desc_) |
Definition at line 189 of file northbridge.c.
anonymous enum |
Enumerator | |
---|---|
TOM_REG | |
TOUUD_REG | |
MESEG_BASE_REG | |
MESEG_LIMIT_REG | |
REMAP_BASE_REG | |
REMAP_LIMIT_REG | |
TOLUD_REG | |
BGSM_REG | |
BDSM_REG | |
TSEG_REG | |
NUM_MAP_ENTRIES |
Definition at line 191 of file northbridge.c.
Definition at line 357 of file northbridge.c.
References ARRAY_SIZE, BIOS_DEBUG, DEVEN, DEVEN_D1F0EN, DEVEN_D1F1EN, DEVEN_D1F2EN, DEVEN_D2EN, DEVEN_D3EN, DEVEN_D4EN, DEVEN_D7EN, device::enabled, mask, name, PCI_DEVFN, pci_read_config32(), pci_write_config32(), pcidev_on_root(), pcidev_path_on_root(), and printk.
Referenced by northbridge_init().
Definition at line 570 of file northbridge.c.
References cpu_bus_ops, DEVICE_PATH_CPU_CLUSTER, DEVICE_PATH_DOMAIN, device::ops, device::path, pci_domain_ops, and device_path::type.
Definition at line 45 of file northbridge.c.
References base, and pci_read_config32().
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Definition at line 63 of file northbridge.c.
References base, and mchbar_read32().
Definition at line 393 of file northbridge.c.
References epbar_read16(), epbar_write32(), EPPVCCAP1, EPVC0RCTL, EPVC1RCTL, and EPVC1RSTS.
Referenced by northbridge_init().
Definition at line 238 of file northbridge.c.
References resource::base, BGSM_REG, BIOS_DEBUG, DPR, resource::flags, IORESOURCE_ASSIGNED, IORESOURCE_CACHEABLE, IORESOURCE_FIXED, IORESOURCE_MEM, IORESOURCE_RESERVE, IORESOURCE_STORED, KiB, mc_read_map_entries(), mc_report_map_entries(), MiB, mmio_resource, new_resource(), NUM_MAP_ENTRIES, pci_read_config32(), printk, ram_resource, dpr_register::raw, reserved_ram_resource, resource::size, dpr_register::size, TOLUD_REG, TOUUD_REG, and TSEG_REG.
Referenced by mc_read_resources().
Definition at line 93 of file northbridge.c.
References ARRAY_SIZE, resource::base, base, BIOS_DEBUG, resource::flags, resource::index, fixed_mmio_descriptor::index, IORESOURCE_ASSIGNED, IORESOURCE_FIXED, IORESOURCE_MEM, IORESOURCE_RESERVE, IORESOURCE_STORED, mc_fixed_resources, mmconf_resource(), new_resource(), PCIEXBAR, printk, resource::size, and fixed_mmio_descriptor::size.
Referenced by mc_read_resources().
Definition at line 219 of file northbridge.c.
References memory_map, NUM_MAP_ENTRIES, and read_map_entry().
Referenced by mc_add_dram_resources().
Definition at line 332 of file northbridge.c.
References CAPID0_A, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, KiB, mc_add_dram_resources(), mc_add_fixed_mmio_resources(), mmio_resource, pci_dev_read_resources(), pci_read_config32(), VTD_DISABLE, VTVC0_BASE_ADDRESS, and VTVC0_BASE_SIZE.
Definition at line 227 of file northbridge.c.
References BIOS_DEBUG, map_entry::description, GGC, memory_map, NUM_MAP_ENTRIES, pci_read_config16(), and printk.
Referenced by mc_add_dram_resources().
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Definition at line 21 of file northbridge.c.
References device::bus, pci_path::devfn, DEVICE_PATH_DOMAIN, DEVICE_PATH_PCI, NULL, device::path, device_path::pci, PCI_DEVFN, bus::secondary, and device_path::type.
Definition at line 409 of file northbridge.c.
References CONFIG, DMI_AFE_PM_TMR, dmibar_clrsetbits32(), dmibar_setbits16, dmibar_setbits32, dmibar_write32(), DMICESTS, DMIL0SLAT, DMILCTL, DMILCTL2, DMILLTC, and DMIUESTS.
Referenced by northbridge_init().
Definition at line 505 of file northbridge.c.
Definition at line 482 of file northbridge.c.
References BIOS_DEBUG, BIOS_RESET_CPL, disable_devices(), init_egress(), INTRDIRCTL, mchbar_clrsetbits8(), mchbar_setbits8, mdelay(), northbridge_dmi_init(), northbridge_topology_init(), printk, and set_power_limits().
Definition at line 434 of file northbridge.c.
References dmibar_clrsetbits32(), dmibar_setbits32, dmibar_write32(), DMIESD, DMILCAP, DMILE1A, DMILE1D, DMILE2A, DMILE2D, DMIPVCCAP1, device::enabled, epbar_clrsetbits32(), epbar_write32(), EPESD, EPLE1A, EPLE1D, EPLE2A, EPLE2D, EPLE3A, EPLE3D, EPLE4A, EPLE4D, PCI_DEV, pci_or_config32(), pci_update_config32(), pci_write_config32(), pcidev_on_root(), PEG_DCAP2, PEG_ESD, PEG_LE1A, and PEG_LE1D.
Referenced by northbridge_init().
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Definition at line 154 of file northbridge.c.
Referenced by mc_read_map_entries().
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Definition at line 547 of file northbridge.c.
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Definition at line 547 of file northbridge.c.
Referenced by enable_dev().
struct fixed_mmio_descriptor mc_fixed_resources[] |
Definition at line 63 of file northbridge.c.
Referenced by mc_add_fixed_mmio_resources().
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Definition at line 505 of file northbridge.c.
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Definition at line 547 of file northbridge.c.
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Definition at line 154 of file northbridge.c.
Referenced by get_srat_memory_entries(), mc_read_map_entries(), mc_report_map_entries(), and program_total_memory_map().
struct chip_operations northbridge_intel_haswell_ops |
Definition at line 570 of file northbridge.c.
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Definition at line 21 of file northbridge.c.
Referenced by enable_dev().