coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
smihandler.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
device/pci_ops.h
>
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#include <
console/console.h
>
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#include <
cpu/x86/smm.h
>
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#include <soc/nvs.h>
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#include <
southbridge/intel/bd82x6x/pch.h
>
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#include <
southbridge/intel/bd82x6x/me.h
>
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#include <
southbridge/intel/common/pmbase.h
>
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#include <
northbridge/intel/sandybridge/sandybridge.h
>
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/* Include EC functions */
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#include <
ec/quanta/it8518/ec.h
>
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#include "
ec.h
"
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static
u8
mainboard_smi_ec
(
void
)
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{
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u8
cmd =
ec_it8518_get_event
();
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switch
(cmd) {
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case
EC_SMI_LID_CLOSED
:
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printk
(
BIOS_DEBUG
,
"LID CLOSED, SHUTDOWN\n"
);
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/* Go to S5 */
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write_pmbase32
(
PM1_CNT
,
read_pmbase32
(
PM1_CNT
) | (0xf << 10));
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break
;
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}
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return
cmd;
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}
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void
mainboard_smi_gpi
(
u32
gpi_sts)
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{
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if
(gpi_sts & (1 <<
EC_SMI_GPI
)) {
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/* Process all pending events */
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while
(
mainboard_smi_ec
() != 0);
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}
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}
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void
mainboard_smi_sleep
(
u8
slp_typ)
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{
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/*
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* Tell the EC to Enable USB power for S3 if requested.
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* Bit0 of 0x0D/Bit0 of 0x26
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* 0/0 All USB port off
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* 1/0 USB on, all USB port didn't support wake up
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* 0/1 USB on, yellow port support wake up charge, but may not support
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* charge smart phone.
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* 1/1 USB on, yellow port in AUTO mode and didn't support wake up system.
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*/
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if
(
gnvs
->
s3u0
!= 0 ||
gnvs
->
s3u1
!= 0) {
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ec_write
(
EC_PERIPH_CNTL_3
,
ec_read
(
EC_PERIPH_CNTL_3
) | 0x00);
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ec_write
(
EC_USB_S3_EN
,
ec_read
(
EC_USB_S3_EN
) | 0x01);
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printk
(
BIOS_DEBUG
,
"USB wake from S3 enabled.\n"
);
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}
else
{
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/*
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* If USB charging in suspend is disabled then also disable
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* the XHCI PME to prevent wake when the port power is cut
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* after the transition into suspend.
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*/
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if
(
gnvs
->
xhci
) {
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u32
reg32 =
pci_read_config32
(
PCH_XHCI_DEV
, 0x74);
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reg32 &= ~(1 << 8);
/* disable PME */
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reg32 |= (1 << 15);
/* clear PME status */
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pci_write_config32
(
PCH_XHCI_DEV
, 0x74, reg32);
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}
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}
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ec_kbc_write_cmd
(
EC_KBD_CMD_MUTE
);
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ec_it8518_enable_wake_events
();
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}
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int
mainboard_smi_apmc
(
u8
apmc)
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{
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switch
(apmc) {
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case
APM_CNT_FINALIZE
:
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stout_ec_finalize_smm
();
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break
;
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case
APM_CNT_ACPI_ENABLE
:
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/*
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* TODO(kimarie) Clear all pending events and enable SCI.
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*/
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ec_write_cmd
(
EC_CMD_NOTIFY_ACPI_ENTER
);
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break
;
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case
APM_CNT_ACPI_DISABLE
:
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/*
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* TODO(kimarie) Clear all pending events and enable SMI.
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*/
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ec_write_cmd
(
EC_CMD_NOTIFY_ACPI_EXIT
);
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break
;
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}
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return
0;
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}
PM1_CNT
#define PM1_CNT
Definition:
pm.h:27
printk
#define printk(level,...)
Definition:
stdlib.h:16
console.h
mainboard_smi_sleep
void __weak mainboard_smi_sleep(u8 slp_typ)
Definition:
smihandler.c:210
mainboard_smi_apmc
int __weak mainboard_smi_apmc(u8 data)
Definition:
smihandler.c:209
mainboard_smi_gpi
void __weak mainboard_smi_gpi(u32 gpi_sts)
Definition:
smihandler.c:208
ec_read
u8 ec_read(u8 addr)
Definition:
ec.c:107
ec_write
int ec_write(u8 addr, u8 data)
Definition:
ec.c:115
ec_kbc_write_cmd
void ec_kbc_write_cmd(u8 cmd)
Definition:
ec.c:77
ec_write_cmd
void ec_write_cmd(u8 cmd)
Definition:
ec.c:79
ec_it8518_get_event
u8 ec_it8518_get_event(void)
Definition:
ec.c:109
ec_it8518_enable_wake_events
void ec_it8518_enable_wake_events(void)
Definition:
ec.c:123
ec.h
EC_USB_S3_EN
#define EC_USB_S3_EN
Definition:
ec.h:51
EC_KBD_CMD_MUTE
#define EC_KBD_CMD_MUTE
Definition:
ec.h:27
EC_CMD_NOTIFY_ACPI_EXIT
#define EC_CMD_NOTIFY_ACPI_EXIT
Definition:
ec.h:46
EC_PERIPH_CNTL_3
#define EC_PERIPH_CNTL_3
Definition:
ec.h:50
EC_CMD_NOTIFY_ACPI_ENTER
#define EC_CMD_NOTIFY_ACPI_ENTER
Definition:
ec.h:45
smm.h
APM_CNT_ACPI_DISABLE
#define APM_CNT_ACPI_DISABLE
Definition:
smm.h:21
APM_CNT_ACPI_ENABLE
#define APM_CNT_ACPI_ENABLE
Definition:
smm.h:22
APM_CNT_FINALIZE
#define APM_CNT_FINALIZE
Definition:
smm.h:24
pci_ops.h
pci_write_config32
static __always_inline void pci_write_config32(const struct device *dev, u16 reg, u32 val)
Definition:
pci_ops.h:76
pci_read_config32
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition:
pci_ops.h:58
BIOS_DEBUG
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition:
loglevel.h:128
EC_SMI_GPI
#define EC_SMI_GPI
Definition:
ec.h:10
stout_ec_finalize_smm
void stout_ec_finalize_smm(void)
Definition:
ec.c:41
EC_SMI_LID_CLOSED
#define EC_SMI_LID_CLOSED
Definition:
ec.h:9
mainboard_smi_ec
static u8 mainboard_smi_ec(void)
Definition:
smihandler.c:16
ec.h
read_pmbase32
u32 read_pmbase32(const u8 addr)
Definition:
pmbase.c:57
write_pmbase32
void write_pmbase32(const u8 addr, const u32 val)
Definition:
pmbase.c:36
pmbase.h
sandybridge.h
gnvs
struct global_nvs * gnvs
Definition:
smm_module_handler.c:100
me.h
pch.h
PCH_XHCI_DEV
#define PCH_XHCI_DEV
Definition:
pch.h:88
u32
uint32_t u32
Definition:
stdint.h:51
u8
uint8_t u8
Definition:
stdint.h:45
global_nvs::s3u0
u8 s3u0
Definition:
nvs.h:34
global_nvs::s3u1
u8 s3u1
Definition:
nvs.h:35
global_nvs::xhci
u8 xhci
Definition:
nvs.h:99
src
mainboard
google
stout
smihandler.c
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