coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
stdint.h
>
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#include <
northbridge/intel/haswell/haswell.h
>
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#include <
northbridge/intel/haswell/raminit.h
>
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#include <
southbridge/intel/lynxpoint/pch.h
>
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#include <
option.h
>
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#include <
ec/lenovo/pmh7/pmh7.h
>
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#include <
device/pci_ops.h
>
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void
mainboard_config_rcba
(
void
)
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{
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RCBA16
(
D31IR
) =
DIR_ROUTE
(
PIRQA
,
PIRQD
,
PIRQC
,
PIRQA
);
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RCBA16
(
D29IR
) =
DIR_ROUTE
(
PIRQH
,
PIRQD
,
PIRQA
,
PIRQC
);
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RCBA16
(
D28IR
) =
DIR_ROUTE
(
PIRQA
,
PIRQA
,
PIRQA
,
PIRQA
);
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RCBA16
(
D27IR
) =
DIR_ROUTE
(
PIRQG
,
PIRQB
,
PIRQC
,
PIRQD
);
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RCBA16
(
D26IR
) =
DIR_ROUTE
(
PIRQA
,
PIRQF
,
PIRQC
,
PIRQD
);
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RCBA16
(
D25IR
) =
DIR_ROUTE
(
PIRQE
,
PIRQF
,
PIRQG
,
PIRQH
);
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RCBA16
(
D22IR
) =
DIR_ROUTE
(
PIRQA
,
PIRQB
,
PIRQC
,
PIRQD
);
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RCBA16
(
D20IR
) =
DIR_ROUTE
(
PIRQA
,
PIRQB
,
PIRQC
,
PIRQD
);
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}
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void
mb_late_romstage_setup
(
void
)
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{
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u8
enable_peg =
get_uint_option
(
"enable_dual_graphics"
, 0);
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bool
power_en =
pmh7_dgpu_power_state
();
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if
(enable_peg != power_en)
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pmh7_dgpu_power_enable
(!power_en);
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if
(!enable_peg) {
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// Hide disabled dGPU device
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pci_and_config32
(
HOST_BRIDGE
,
DEVEN
, ~
DEVEN_D1F0EN
);
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}
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}
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void
mb_get_spd_map
(
struct
spd_info
*spdi)
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{
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spdi->
addresses
[0] = 0x50;
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spdi->
addresses
[2] = 0x51;
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}
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const
struct
usb2_port_config
mainboard_usb2_ports
[
MAX_USB2_PORTS
] = {
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/* Length, Enable, OCn#, Location */
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{ 0x0040, 1, 0,
USB_PORT_BACK_PANEL
},
/* USB3 */
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{ 0x0040, 1, 0,
USB_PORT_BACK_PANEL
},
/* USB3 */
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{ 0x0110, 1, 1,
USB_PORT_BACK_PANEL
},
/* USB2 charge */
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{ 0x0040, 1,
USB_OC_PIN_SKIP
,
USB_PORT_BACK_PANEL
},
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{ 0x0080, 1,
USB_OC_PIN_SKIP
,
USB_PORT_DOCK
},
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{ 0x0080, 1, 2,
USB_PORT_BACK_PANEL
},
/* USB2 */
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{ 0x0040, 1, 3,
USB_PORT_BACK_PANEL
},
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{ 0x0040, 1, 3,
USB_PORT_BACK_PANEL
},
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{ 0x0040, 1, 4,
USB_PORT_BACK_PANEL
},
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{ 0x0110, 1, 4,
USB_PORT_BACK_PANEL
},
/* WWAN */
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{ 0x0040, 1, 5,
USB_PORT_INTERNAL
},
/* WLAN */
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{ 0x0040, 1, 5,
USB_PORT_BACK_PANEL
},
/* webcam */
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{ 0x0080, 1, 6,
USB_PORT_BACK_PANEL
},
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{ 0x0040, 1, 6,
USB_PORT_BACK_PANEL
},
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};
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const
struct
usb3_port_config
mainboard_usb3_ports
[
MAX_USB3_PORTS
] = {
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{ 1, 0 },
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{ 1, 0 },
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{ 1,
USB_OC_PIN_SKIP
},
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{ 1,
USB_OC_PIN_SKIP
},
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{ 1, 1 },
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{ 1, 1 },
/* WWAN */
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};
PIRQH
#define PIRQH
Definition:
irq.h:101
PIRQC
#define PIRQC
Definition:
irq.h:96
PIRQA
#define PIRQA
Definition:
irq.h:94
PIRQD
#define PIRQD
Definition:
irq.h:97
PIRQB
#define PIRQB
Definition:
irq.h:95
PIRQF
#define PIRQF
Definition:
irq.h:99
PIRQE
#define PIRQE
Definition:
irq.h:98
PIRQG
#define PIRQG
Definition:
irq.h:100
raminit.h
DEVEN_D1F0EN
#define DEVEN_D1F0EN
Definition:
host_bridge.h:21
DEVEN
#define DEVEN
Definition:
host_bridge.h:16
pci_ops.h
pci_and_config32
static __always_inline void pci_and_config32(const struct device *dev, u16 reg, u32 andmask)
Definition:
pci_ops.h:158
mainboard_usb3_ports
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS]
Definition:
romstage.c:45
mainboard_config_rcba
void mainboard_config_rcba(void)
Definition:
romstage.c:7
mb_get_spd_map
void mb_get_spd_map(struct spd_info *spdi)
Definition:
romstage.c:19
mainboard_usb2_ports
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS]
Definition:
romstage.c:27
mb_late_romstage_setup
void mb_late_romstage_setup(void)
Definition:
romstage.c:23
haswell.h
get_uint_option
unsigned int get_uint_option(const char *name, const unsigned int fallback)
Definition:
option.c:116
option.h
pmh7_dgpu_power_state
bool pmh7_dgpu_power_state(void)
Definition:
pmh7.c:69
pmh7_dgpu_power_enable
void pmh7_dgpu_power_enable(int onoff)
Definition:
pmh7.c:54
pmh7.h
USB_OC_PIN_SKIP
#define USB_OC_PIN_SKIP
Definition:
pei_data.h:27
MAX_USB3_PORTS
#define MAX_USB3_PORTS
Definition:
pei_data.h:26
USB_PORT_BACK_PANEL
@ USB_PORT_BACK_PANEL
Definition:
pei_data.h:30
USB_PORT_DOCK
@ USB_PORT_DOCK
Definition:
pei_data.h:32
USB_PORT_INTERNAL
@ USB_PORT_INTERNAL
Definition:
pei_data.h:35
MAX_USB2_PORTS
#define MAX_USB2_PORTS
Definition:
pei_data.h:25
D20IR
#define D20IR
Definition:
rcba.h:96
D31IR
#define D31IR
Definition:
rcba.h:87
D26IR
#define D26IR
Definition:
rcba.h:92
D28IR
#define D28IR
Definition:
rcba.h:90
D22IR
#define D22IR
Definition:
rcba.h:95
D25IR
#define D25IR
Definition:
rcba.h:93
DIR_ROUTE
#define DIR_ROUTE(a, b, c, d)
Definition:
rcba.h:116
D29IR
#define D29IR
Definition:
rcba.h:89
D27IR
#define D27IR
Definition:
rcba.h:91
HOST_BRIDGE
@ HOST_BRIDGE
Definition:
reg_access.h:23
RCBA16
#define RCBA16(x)
Definition:
rcba.h:13
pch.h
stdint.h
u8
uint8_t u8
Definition:
stdint.h:45
spd_info
Definition:
spd.h:11
spd_info::addresses
uint8_t addresses[4]
Definition:
raminit.h:11
usb2_port_config
Definition:
usb.h:27
usb3_port_config
Definition:
usb.h:130
src
mainboard
lenovo
t440p
romstage.c
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