coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
chip.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pci.h>
7 #include <soc/acpi.h>
8 #include <soc/cpu.h>
9 #include <soc/data_fabric.h>
10 #include <soc/iomap.h>
11 #include <soc/pci_devs.h>
12 #include <soc/southbridge.h>
13 #include "chip.h"
14 #include <fsp/api.h>
15 
16 /* Supplied by i2c.c */
18 /* Supplied by uart.c */
20 
23  .set_resources = noop_set_resources,
24  .init = mp_cpu_bus_init,
25  .acpi_fill_ssdt = generate_cpu_entries,
26 };
27 
28 static const char *soc_acpi_name(const struct device *dev)
29 {
30  if (dev->path.type == DEVICE_PATH_DOMAIN)
31  return "PCI0";
32 
33  if (dev->path.type != DEVICE_PATH_PCI)
34  return NULL;
35 
36  printk(BIOS_WARNING, "Unknown PCI device: dev: %d, fn: %d\n",
37  PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
38  return NULL;
39 };
40 
41 static struct device_operations pci_domain_ops = {
43  .set_resources = pci_domain_set_resources,
44  .scan_bus = pci_domain_scan_bus,
45  .acpi_name = soc_acpi_name,
46 };
47 
48 static void set_mmio_dev_ops(struct device *dev)
49 {
50  switch (dev->path.mmio.addr) {
51  case APU_I2C2_BASE:
52  case APU_I2C3_BASE:
53  case APU_I2C4_BASE:
54  dev->ops = &soc_amd_i2c_mmio_ops;
55  break;
56  case APU_UART0_BASE:
57  case APU_UART1_BASE:
58  case APU_UART2_BASE:
59  case APU_UART3_BASE:
60  dev->ops = &picasso_uart_mmio_ops;
61  break;
62  }
63 }
64 
65 static void enable_dev(struct device *dev)
66 {
67  /* Set the operations if it is a special bus type */
68  switch (dev->path.type) {
69  case DEVICE_PATH_DOMAIN:
70  dev->ops = &pci_domain_ops;
71  break;
73  dev->ops = &cpu_bus_ops;
74  break;
75  case DEVICE_PATH_MMIO:
76  set_mmio_dev_ops(dev);
77  break;
78  default:
79  break;
80  }
81 }
82 
83 static void soc_init(void *chip_info)
84 {
86 
88 
90  fch_init(chip_info);
91 }
92 
93 static void soc_final(void *chip_info)
94 {
95  fch_final(chip_info);
96 }
97 
99  CHIP_NAME("AMD Picasso SOC")
100  .enable_dev = enable_dev,
101  .init = soc_init,
102  .final = soc_final
103 };
#define APU_UART0_BASE
Definition: iomap.h:19
#define APU_I2C3_BASE
Definition: iomap.h:17
#define APU_UART1_BASE
Definition: iomap.h:20
#define APU_I2C2_BASE
Definition: iomap.h:16
void data_fabric_set_mmio_np(void)
Definition: data_fabric.c:15
void fch_init(void *chip_info)
Definition: fch.c:290
void fch_final(void *chip_info)
Definition: fch.c:304
#define printk(level,...)
Definition: stdlib.h:16
void generate_cpu_entries(const struct device *device)
Definition: acpi.c:334
void fsp_silicon_init(void)
Definition: silicon_init.c:242
#define CHIP_NAME(X)
Definition: device.h:32
static void noop_read_resources(struct device *dev)
Standard device operations function pointers shims.
Definition: device.h:73
static void noop_set_resources(struct device *dev)
Definition: device.h:74
static void mp_cpu_bus_init(struct device *dev)
Definition: device.h:240
#define BIOS_WARNING
BIOS_WARNING - Bad configuration.
Definition: loglevel.h:86
static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
Definition: northbridge.c:701
@ DEVICE_PATH_PCI
Definition: path.h:9
@ DEVICE_PATH_CPU_CLUSTER
Definition: path.h:14
@ DEVICE_PATH_DOMAIN
Definition: path.h:13
@ DEVICE_PATH_MMIO
Definition: path.h:21
#define PCI_FUNC(devfn)
Definition: pci_def.h:550
#define PCI_SLOT(devfn)
Definition: pci_def.h:549
void pci_domain_read_resources(struct device *dev)
Definition: pci_device.c:547
void pci_domain_set_resources(struct device *dev)
Definition: pci_device.c:564
void pci_domain_scan_bus(struct device *dev)
Scan a PCI domain.
Definition: pci_device.c:1610
struct device_operations default_dev_ops_root
Default device operation for root device.
Definition: root_device.c:123
struct device_operations cpu_bus_ops
Definition: chip.c:22
struct device_operations soc_amd_i2c_mmio_ops
Definition: i2c.c:123
struct chip_operations soc_amd_picasso_ops
Definition: chip.c:98
static struct device_operations pci_domain_ops
Definition: chip.c:41
static void enable_dev(struct device *dev)
Definition: chip.c:65
static void soc_init(void *chip_info)
Definition: chip.c:83
struct device_operations picasso_uart_mmio_ops
Definition: uart.c:111
static const char * soc_acpi_name(const struct device *dev)
Definition: chip.c:28
static void set_mmio_dev_ops(struct device *dev)
Definition: chip.c:48
static void soc_final(void *chip_info)
Definition: chip.c:93
#define NULL
Definition: stddef.h:19
void(* read_resources)(struct device *dev)
Definition: device.h:39
struct mmio_path mmio
Definition: path.h:128
struct pci_path pci
Definition: path.h:116
enum device_path_type type
Definition: path.h:114
Definition: device.h:107
struct device_path path
Definition: device.h:115
struct device_operations * ops
Definition: device.h:143
uintptr_t addr
Definition: path.h:106
unsigned int devfn
Definition: path.h:54